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A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias ( V\mathrm{ G} )/positive drain bias ( V\mathrm{ D} ) in amorphous hafnium-indium–zinc-oxide thin-film transistors. Negative threshold voltage ( V\mathrm {\mathbf {th}} ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of ( V\mathrm{G}= -5 V, V\mathrm{D}= 15 V, and V\mathrm{ S}= 0 V) and ( V\mathrm{G}= -5 V, V\mathrm{D}= 0 V, and V\mathrm{S}= 15 V) under light illumination, it is found that the negative V\mathrm {\mathbf {th}} shift is affected only by V\mathbf {G} , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by V\mathrm{D} -induced drain-side trapped holes. Furthermore, the drain-side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance ( C\mathrm {\mathbf {GD}} ) was measured before/after the ( V\mathrm{G}= -5 V, V\mathrm{D}= 15 V, and V\mathrm{S}= 0 V) stress to clarify the presence and distribution of the drain-side trapped holes. From C\mathrm {\mathbf {GD}} stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress. [ABSTRACT FROM AUTHOR]

Negative bias-induced instability of amorphous hafnium indium zinc oxide (α-HIZO) thin film transistors (TFTs) was investigated at various temperatures. In order to examine temperature-induced effects, fabricated TFTs with different combinations of gate insulator and gate metal were stressed by a negative gate bias at various temperatures. As a result, it is proved that negative bias-induced hole-trapping in the gate insulators and temperature-enhanced electron injection from the gate metals occurs at the same time at all temperatures, and the instability of HIZO TFT is more affected by the dominant factor out of the two mechanisms. [ABSTRACT FROM AUTHOR]

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator. [ABSTRACT FROM AUTHOR]