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Your search keyword '"Winstead, Chris"' showing total 4 results
Start Over Author "Winstead, Chris" Topic analog decoding
4 results on '"Winstead, Chris"'

1. Design for Testability of CMOS Analog Sum-Product Error-Control Decoders.

Author

Mimi Yiu, Winstead, Chris, Gaudet, Vincent, and Schiegel, Christian

Abstract

A built-in self-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation. [ABSTRACT FROM AUTHOR]

Published
2007
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2. Low-Voltage CMOS Circuits for Analog Iterative Decoders.

Author

Winstead, Chris, Nguyen, Nhan, Gaudet, Vincent C., and Schlegel, Christian

Subjects
*COMPLEMENTARY metal oxide semiconductors, *DECODERS (Electronics), *COMMUNICATION, *ELECTRIC potential, *ALGORITHMS, *DIGITAL electronics
Abstract

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented. [ABSTRACT FROM AUTHOR]

Published
2006
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3. A dual-function mixed-signal circuit for LDPC encoding/decoding

Author

Haley, David, Gaudet, Vincent, Winstead, Chris, Grant, Alex, and Schlegel, Christian

Subjects
*FENCES, *WIRELESS communications, *COMPLEMENTARY metal oxide semiconductors, *BROADBAND communication systems
Abstract

Abstract: We present a low power, dual-function encode/decode circuit for a class of reversible low-density parity-check codes. The circuit offers a small silicon footprint, by operating as an analog decoder and reusing resources to switch into a digital encode mode. In order to achieve this behaviour from a single circuit we have developed mode-switching gates. These logic gates are able to switch between analog (soft) and digital (hard) computation. Only a small overhead in circuit area is required to transform the analog decoder into a full codec. The encode operation can be performed two orders of magnitude faster than the decode operation, making the circuit suitable for full-duplex applications. The low power and small area of the circuit make it an attractive option for battery powered wireless devices. Circuit simulations indicate a decoding latency of with negligible SNR loss with respect to digital sum–product decoders. [Copyright &y& Elsevier]

Published
2009
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4. A dual-function mixed-signal circuit for LDPC encoding/decoding

Author

Vincent Gaudet, Christian Schlegel, Chris Winstead, David Victor Lawrie Haley, Alex Grant, Haley, David Victor Lawrie, Gaudet, Vincent, Winstead, Chris, Grant, Alexander James, and Schlegel, Christian

Subjects
LDPC codes, Computer science, iterative decoding/encoding, Mixed-signal integrated circuit, Diode-or circuit, Data_CODINGANDINFORMATIONTHEORY, Circuit extraction, iterative decoding, Computer Science::Hardware Architecture, Computer Science::Emerging Technologies, analog decoding, Hardware and Architecture, Logic gate, subthreshold CMOS, Electronic engineering, Codec, Electrical and Electronic Engineering, Low-density parity-check code, Software, Decoding methods, Computer Science::Information Theory, Asynchronous circuit
Abstract

We present a low power, dual-function encode/decode circuit for a class of reversible low-density parity-check codes. The circuit offers a small silicon footprint, by operating as an analog decoder and reusing resources to switch into a digital encode mode. In order to achieve this behaviour from a single circuit we have developed mode-switching gates. These logic gates are able to switch between analog (soft) and digital (hard) computation. Only a small overhead in circuit area is required to transform the analog decoder into a full codec. The encode operation can be performed two orders of magnitude faster than the decode operation, making the circuit suitable for full-duplex applications. The low power and small area of the circuit make it an attractive option for battery powered wireless devices. Circuit simulations indicate a decoding latency of 10@ms with negligible SNR loss with respect to digital sum-product decoders.

Published
2009

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