1. Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area.
- Author
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Wang, Guan Cheng, Zhu, Yan, Chan, Chi-Hang, U, Seng-Pan, and Martins, Rui P.
- Subjects
SUCCESSIVE approximation analog-to-digital converters ,DIGITAL-to-analog converters ,CMOS memory circuits ,MATHEMATICAL models ,SIGNAL generators - Abstract
This paper presents two calibration schemes to correct the stage gain error in analog-to-digital converters. The two approaches target different scenarios, either better calibration accuracy or less digital overhead. First, we optimize the gain calculation scheme in the conventional code statistics-based approach, which improves the calibration accuracy. Moreover, we introduce a missing-code-detected calibration that replaces the calculation of the gain coefficient by counting and multiplying the number of missing codes in the digital domain, which significantly simplifies the digital implementation. To eliminate the calibration dependence on the input signal, we implement a testing signal generation on-chip. We also compare these calibration schemes with the requirements of the input signal, the calibration accuracy, as well as the hardware overhead based on a mathematical model with behavior simulations. Both concepts were verified in an 11-bit 80-MS/s successive approximation register with a bridge digital-to-analog converter fabricated in a 65-nm CMOS. [ABSTRACT FROM AUTHOR]
- Published
- 2018
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