Search

A novel 0-2 Multi-Stage Noise Shaping (MASH) analogue-to-digital converter (ADC) is proposed. The first stage is implemented using a 4-bit SAR ADC. The second stage uses a voltage controlled oscillator (VCO)-based quantiser (VCOQ). Unlike earlier VCOQs which provide first-order noise shaping, the VCOQ proposed in this Letter achieves second-order noise filtering. To implement this noise shaping, the quantisation noise of the VCOQ is extracted as a pulse-width-modulated signal, and it is fed back to the VCO input using a charge pump circuit. In the proposed scheme, the input signal to the VCO is small. Therefore, the linearity requirement of this block is relaxed. Also, any error related to the charge pump circuitry will be first-order shaped at the output. Simulation results confirm the second-order noise shaping of the output of the ADC, and an excellent (14-bit signal-to-noise and distortion ratio) performance with the over-sampling ratio of 16. [ABSTRACT FROM AUTHOR]

A new architecture is proposed which reduces the power consumption and capacitor area in successive approximation register (SAR) analogue-to-digital converters (ADCs). Two identical capacitor-splitting capacitor arrays are used in a two-step process for quantisation, and this significantly reduces the switching power and capacitor area. [ABSTRACT FROM AUTHOR]

A power efficient noise-coupled ΔΣ analogue-to-digital converter (ADC) is proposed. The new architecture can effectively implement double-noise coupling with simple digital delay cells. For performance improvement, one more input feed-forward path is added to reduce the output swing of an integrator. Zero optimisation technique was also applied to the proposed modulator to increase the signal to quantisation noise ratio (SQNR). A third-order ΔΣ ADC using new configuration was designed and simulated. The results verify the advantages of the proposed architecture. [ABSTRACT FROM AUTHOR]

Extended-counting A/D converters are proposed which achieve a high accuracy by performing the conversion in several cycles. During the first cycle, the circuit performs as an incremental ADC, while during the remaining ones it acts as a multi-slope counting converter. With only one opamp and a single-slope ADC, the accuracy is comparable to that of a second-order incremental ADC. A three-step A/D converter using only a single opamp and a two-slope ADC achieves an accuracy comparable to that of a third-order incremental ADC, but with much higher power efficiency. [ABSTRACT FROM AUTHOR]