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An analytical model for a novel triple reduced surface field (RESURF) lateral double-diffused metal–oxide–semiconductor (LDMOS) field-effect transistor with a low on-resistance n-type top (N-top) layer is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF LDMOS is presented by solving the 2-D Poisson’s equation, which can also be applied in single, double, and conventional triple RESURF structures. The vertical and lateral breakdown voltages are formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of the N-top layer ( Q\textrm {ntop} ) is derived which can give a guidance for the dose of N-top layer. The triple RESURF LDMOS with a low on-resistance N-top layer is designed and manufactured according to the analytical model. All the analytical results can be well verified by numerical and measured results, showing the validity of the presented model. [ABSTRACT FROM AUTHOR]

3-D edge termination design and analytic model for specific on-resistance ( R \mathrm{\scriptscriptstyle ON,\text {sp}}) versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters L1 and L2 in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at L1 = 30~\mu \text{m} and L2 = 1~\mu \text{m} . On the other hand, an analytic model is developed to describe the relation between R \mathrm{\scriptscriptstyle ON,\text {sp}} and BV, which is obtained as R \mathrm{\scriptscriptstyle ON,\text {sp}} = 5.93 \times 10^{-6} \times 22({T}/298)^{1.7} \times \text {BV}^{2} and theoretically verifies that the fabricated device has achieved optimized R \mathrm{\scriptscriptstyle ON,\text {sp}} and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with R \mathrm{\scriptscriptstyle ON,\text {sp}} of 86.49 \textm\Omega ~\cdot cm2 and BV of 805 V, which is leading performance for the 700-V applications in published data. [ABSTRACT FROM AUTHOR]