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Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface traps and short channel effects-dependent back gate capability in the UTBB FDSOI device are proposed. The developed model allows the accurate assessment of body factor (γ) with the dependence of front/back interface trap density in the ultrascaled FDSOI device, taking the impact of gate area scaling as well as quantum effects into account. It also facilitates the evaluation of back bias effectiveness variability induced by interface traps and benefits the dynamic threshold voltage strategy in terms of adaptive back-biasing for performance optimization, which is consistent with 3-D device simulations and measurements. Moreover, the results confirm that γ variability follows Pelgrom’s rule. [ABSTRACT FROM AUTHOR]

Aggressively scaled devices with high power density wrapped around the low thermal conductivity material in narrow space are susceptible to self-heating effect, which includes serious mutual-heating due to proximity effect in multifinger/fin FETs. Obtaining local temperature instead of equivalent lumped temperature at device/circuit level quickly is crucial for designers to accurately predict front-end-of-line reliability (i.e., hot carrier injection, bias temperature instability, and time dependent dielectric breakdown) and achieve better thermal management. In this paper, we: 1) first propose an analytical model based on multistage thermal network to address effectively the self- and mutual-heating within the device; 2) validate the multistage network and proposed analytical model by COMSOL and SPICE simulation, respectively; and 3) utilize the model to investigate local temperature rise in multifinger and multifin FETs-based inverter and ring oscillator as well as provide thermal-aware IC design guideline for self-heating and reliability optimization. The results show that the analytical multistage thermal model can predict local temperature rise and quantify nonuniform temperature difference in full-frequency range, superior to the lumped thermal model. Moreover, the model can offer quick thermal analysis at the pre-Si stage for reliability prediction and thermal-aware design. [ABSTRACT FROM AUTHOR]