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We present a method to emulate a leaky integrate-and-fire (LIF) model in a field-programmable gate array (FPGA) in a hardware-efficient manner. The simplified spike-response model (SRM0) is chosen as an LIF model. For the hardware-efficient implementation of SRM0, we adopt the template-scaling-based exponential function approximation (TS-EFA). This method allows high precision and low latency exponential function approximations with the efficient use of hardware resources. We subsequently propose an algorithm for SRM0, which leverages the advantage of TS-EFA. An implementation of 512 neurons conforming to SRM0 in an FPGA highlights (i) high precision of SRM0 emulation (mean squared error of membrane potential approximation: $4\times 10^{-12} - 1\times 10^{-10}$), (ii) low latency (eight clock cycles), and (iii) high efficiency in hardware usage (only 125b memory per neuron). [ABSTRACT FROM AUTHOR]