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Functional Verification is one of the main processes in the Research and Development of new System-on-Chip. As chips are becoming more and more complex, this step becomes an extensive bottleneck which can vastly delay the chip mass production. It is a mandatory step as the design needs to not contain any faults, to ensure proper functioning. If this step is bypassed, large major financial losses and customer dissatisfaction can happen later in the process. Additionally, if the verification process is prolonging for a long period of time, to achieve a higher quality product, it will also cause a financial impact. Therefore, the solution is to find ways to optimize this activity. This paper contains a review on how Artificial Intelligence can reduce this blockage, taking into consideration the time spent on implementing the verification environment and the time of attaining the aimed coverage percentage. The engineer will take a decision on which causes of time-consuming processes presented in the paper will be reduced, depending on project specifics and his or her experience. A candidate for optimizing the training of the Neural Network is the Nvidia’s Computer Unified Device Architecture (CUDA). CUDA is parallel computing platform that make use of the GPU, peculiarly of the CUDA cores located inside Nvidia GPUs. [ABSTRACT FROM AUTHOR]