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Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI). In‐memory computing (IMC) offers a high performance and energy‐efficient computing paradigm. To date, in‐memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in‐memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in‐memory electrical current sensing units using spin‐orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state‐of‐the‐art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%. [ABSTRACT FROM AUTHOR]

Hardware implementations of Artificial Neural Networks (ANNs) using conventional binary arithmetic units are computationally expensive and energy-intensive together with large area footprints. Stochastic computing (SC) is an unconventional computing paradigm that operates on stochastic bit streams. It can offer low-power and area-efficient hardware implementations and has shown promising results when applied to ANN hardware circuits. SC relies on stochastic number generators (SNGs) to map input binary numbers to stochastic bit streams. The SNGs are conventionally implemented using random number generators (RNGs) and comparators. Linear feedback shifted registers (LFSRs) are typically used as the RNGs, which need far more area and power than the SC core, counteracting the latter's main advantages. To mitigate this problem, in this Letter, RNGs employing Spin–Orbit Torque (SOT)-induced stochastic switching of perpendicularly magnetized Ta/CoFeB/MgO nanodevices have been proposed. Furthermore, the SOT true random number generator (TRNG) is integrated with the simple CMOS stochastic computing circuits to perform a stochastic artificial neural network. To further optimize power and area efficiency, a fully parallel architecture and TRNG-sharing scheme are presented. The proposed stochastic ANN using the SOT-based TRNG obtains a negligible inference accuracy loss, compared with the binary version, and achieves 9× and 25× improvement in terms of area and power, respectively, compared with the ANN using LFSRs. [ABSTRACT FROM AUTHOR]