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There is a need to design a hardware synapse array appropriate for enhancing the efficiency of neuromorphic computing systems while minimizing energy consumption. This study introduces a memristor device with an AlOx overshoot suppression layer (A‐OSL) to achieve a self‐compliance effect. By optimizing each cell within the 16 × 16 crossbar array, synaptic devices are successfully fabricated with reliable characteristics and 3‐bit multilevel capabilities. In addition, the oxygen composition of TiOx and the annealing conditions are optimized to reduce the forming voltage and minimize the variation in the switching voltage. As a result, stable forming‐free characteristics are obtained through A‐OSL insertion, a reduction in forming voltage, and TiOx oxygen composition optimization. Also, target weights are accurately transferred to the A‐OSL memristor crossbar array and conducted the inference process by applying spike signals to the array following the designated time step. The spiking neural network (SNN) is demonstrated by measuring vector‐matrix multiplication (VMM) of the 16 × 16 crossbar array. The VMM results exhibit a classification accuracy of 90.80% for the MNIST dataset, which is close to the accuracy achieved by software‐based approaches, amounting to 91.85%. [ABSTRACT FROM AUTHOR]

In this study, the "resting-potential-adjustable soft-reset (RSR)" integrate-and-fire neuron model is proposed for higher reliability of hardware-based spiking neural networks (SNNs). Recently, researchers have attempted to implement neuronal models using hardware. However, previously proposed hard-reset (HR) and soft-reset (SR) neuron models are not suitable for hardware implementation for the following reasons. First, it is difficult to compensate for the neuron-threshold variation, which generally occurs in the fabrication processes. Second, they require a negative voltage supply that consumes substantial energy to implement the negative membrane potential (NMP). Third, for the HR and SR neuron models, maintaining the residual membrane potential (RMP) is challenging. The proposed RSR neuron model solves these challenges without any additional systems and algorithms and provides the following advantages: easy compensation for the neuron-threshold variation, significant energy reduction without using a negative voltage supply for the NMP, and precise preservation of the RMP. We discuss the behavior of the RSR neuron model and evaluate performance by comparing the inference results. Even with the neuron-threshold variation within the six-sigma range, the RSR neuron model restores the inference accuracy to the values of artificial neural networks (ANNs) for various datasets (CIFAR-10: 92.74%, SVHN: 95.00%, MNIST: 98.30%). In the case of the CIFAR-10, the RSR neuron model consumes 32.80% lower energy than the SR neuron model. [Display omitted] [ABSTRACT FROM AUTHOR]

Recently, various memory devices have been actively studied as suitable candidates for synaptic devices, which are important memory and computing units in neuromorphic systems. One of the ways to manage these devices is off-chip training, where it is essential to transfer the pretrained weights accurately. Previous studies, however, have a few limitations, such as a lack of consideration of program errors that occur during the transfer process. Although the smaller the program error, the higher the accuracy, the corresponding increase in the program time must be considered. To evaluate the practical applicability, we fabricated Al2O3/TiOx-based resistive random access memory (RRAM) and investigated the effect of program errors on program time and system degradation. It was confirmed that for smaller program errors, the program time was exponentially longer. Furthermore, we examined the effect of variation with respect to the number of quantized weight states (${N}_{state}$) through system-level simulation. We observed that the optimized ${N}_{state}$ varies depending on whether the program error is small or large. This result is meaningful as it experimentally shows the tradeoff between the program error, program time, and system performance. We expect it to be useful in the development of neuromorphic systems. [ABSTRACT FROM AUTHOR]

On-chip learning is an effective method for adjusting artificial neural networks in neuromorphic computing systems by considering hardware intrinsic properties. However, it faces challenges due to hardware nonidealities, such as the nonlinearity of potentiation and depression and limitations on fine weight adjustment. In this study, we propose a threshold learning algorithm for a variation-tolerant ternary neural network in a memristor crossbar array. This algorithm utilizes two tightly separated resistance states in memristive devices to represent weight values. The high-resistance state (HRS) and low-resistance state (LRS) defined as read current of < 0.1 μA and > 1 μA, respectively, were successfully programmed in a 32 × 32 crossbar array, and exhibited half-normal distributions due to the programming method. To validate our approach experimentally, a 64 × 10 single-layer fully connected network were trained in the fabricated crossbar for an 8 × 8 MNIST dataset using the threshold learning algorithm, where the weight value is updated when a gradient determined by backpropagation exceeds a threshold value. Thanks to the large margin between the two states of the memristor, we observed only a 0.42 % drop in classification accuracy compared to the baseline network results. The threshold learning algorithm is expected to alleviate the programming burden and be utilized in variation-tolerant neuromorphic architectures. [ABSTRACT FROM AUTHOR]