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Topological spin textures are the next-generation spintronic building blocks for storing and processing information because of their controllable formation and annihilation. Memory, logic, and neuromorphic computing applications are reported using such devices having 2-D and 3-D spin textures, namely, vortex, skyrmions, localized bullet, and so on. A robust device-to-circuit-to-system level design is required for developing a neural network (NN) or a neuromorphic computing system (NCS) using these spin devices. Hence, in this work, we present a Verilog-A-based analytical model of a vortex spin-torque nano oscillator (V-STNO) for enabling circuit-level simulation. The model presented here is functional for both linear and nonlinear dynamics of the magnetic vortex core. The nonlinear dynamics show the formation and annihilation of the magnetic vortex depending on its critical currents. Furthermore, the developed model is analyzed for the nanopillar’s diameter and free layer thickness variations. Moreover, an investigation of the temperature effect on the device performance for a range of −40°C to 140 °C is carried out. [ABSTRACT FROM AUTHOR]

Artificial intelligence has been demonstrated for numerous applications including image recognition and processing, internet-of-things (IoT), and speech recognition. Recent neural network (NN) architectures escalating to perform these functionalities require deep-learning and deep NN (DNN) implementation. However, the present algorithm and circuit of DNN suffer from area and energy-efficiency. The usage of an energy-efficient and cost-effective binary NN (BNN) can mitigate the performance bottleneck. The basic component of BNN (the XNOR and accumulate module) is capable of replacing the conventional multiply-and-accumulate (MAC) operation. Among various emerging nonvolatile memories (NVMs), spintronics-based devices are attracting attention for the implementation of the aforementioned architectures. Multilevel voltage-controlled spin-orbit torque -based magnetic memory (MV-SOTM) spin device as synapse and voltage-controlled SOTM (V-SOTM) device as spin-neuron are capable of producing an all-spin NN. This article presents advanced XNOR operation using a computing-in-memory (CiM) mechanism wherein both V-SOTM and MV-SOTM (using series and parallel configuration) based synapses are compared. The MV-SOTM design dissipates 35.51% lesser energy as compared to the 1-bit V-SOTM. Further, the 8-bit synaptic crossbar array is implemented using both the devices with two output spin-neurons. These series and parallel MV-SOTM-based synaptic arrays consume 42.22% and 45.12% lesser power, respectively, as compared to 1-bit V-SOTM based synaptic array. Furthermore, the all-spin BNN design demonstrates a handwritten digit recognition application. [ABSTRACT FROM AUTHOR]