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Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even–odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two’s complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global–local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 $\times $ 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5–45.36 TOPS/W under 5-b MACV output. [ABSTRACT FROM AUTHOR]

This letter presents an upgraded winner‐take‐all (WTA) circuit that is capable of operating under low‐voltage supplies. The proposed circuit re‐configures the basic loop of a conventional WTA through an auxiliary transistor to decrease the dropped voltage across the tail current. This reconfiguration creates an additional biasing voltage providing more adjustability. Moreover, the new feedback path decreases the delay compared to the conventional WTA. Both conventional and proposed WTAs were fabricated in the TSMC 0.18 μm CMOS technology. The experimental results show a 29.4 and 33.2 μs reduction in rising and falling times, respectively, for the proposed WTA under a supply voltage of 0.3 V. [ABSTRACT FROM AUTHOR]