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This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process. [ABSTRACT FROM AUTHOR]

A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW. [ABSTRACT FROM AUTHOR]

Supporting a wide operating range for industrial-standard backward-compatible transmitters often results in energy inefficiency. This paper describes an energy-efficient voltage-mode-serializing transmitter with an operating range of up to 32 Gb/s. The proposed transmitter uses a programmable internal supply to set the voltage level for various data rates optimally, thus improving overall energy efficiency. Output swing and pre-emphasis levels are largely adjustable while the constant output impedance is maintained using a dedicated control loop. CMOS-logic-based circuits and quarter-rate clocking enhance the energy efficiency over the entire data rate range, while a P-over-N voltage-mode driver is used to achieve a high maximum output swing. Two supply regulators with replicas provide constant pull-up and pull-down impedances of the output driver. The variable output swing, pre-emphasis, and internal supply are realized by using segmented output drivers and replicas. The proposed transmitter, fabricated in a 65-nm CMOS process, occupies an active area of 0.173 mm2. The prototype chip achieves a wide output swing range of 0.4–1.3 Vppd and an energy efficiency of 2.10–3.45 pJ/bit, across a data rate of 5 –32 Gb/s. [ABSTRACT FROM PUBLISHER]