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This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter (TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully reconfigurable 3-tap baud-spaced feed-forward equalizer (FFE). The TX uses a segmented tailless current mode logic (CML) driver topology. The key architectural and circuit techniques include the thermometer-encoded driver slices, the clock phase selection circuits to perform segment reassignment to different FFE taps, and coarse–fine tuning of the FFE tap weights. The measured energy efficiencies for PAM-4 signaling are 1.33 pJ/b at 128 Gb/s with 1-Vppd output amplitude and 1.0 pJ/b at 112 Gb/s with 0.6-Vppd output amplitude. These results represent the highest data rate and best energy efficiencies reported to date. [ABSTRACT FROM AUTHOR]

We report 50- and 60-Gb/s hybrid-integrated optical links in the O-band with CMOS photonic components driven by silicon–germanium ICs using optical-domain feed-forward equalization. The link includes a segmented-electrode Mach–Zehnder modulator and a Ge photodetector that provide high bandwidths and the potential for tight integration with control and monitoring electronics. The combination of these features enables the demonstration of a 60-Gb/s AC-coupled link and a 50-Gb/s DC-coupled link with bit error rates below 10–12 without the use of forward-error correction codes. This result provides a promising path toward extending speeds in latency sensitive optical links. [ABSTRACT FROM AUTHOR]

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features a look-ahead speculation to relax DFE timing to 4 unit-interval. The analog front end includes a transadmittance transimpedance inductorless variable gain amplifier, resulting in a low power and compact front end. The RX, wirebonded to a discrete GaAs photodiode, achieves an energy efficiency of 1.4 pJ/bit and −5-dBm optical modulation amplitude while recovering PRBS-7 data (bit-error-rate <10^-12 ) modulated by a VCSEL driver with a 2-tap feed forward equalization (FFE) (main + precursor) over 7 m of graded-index 50/125- \mu \textm multimode fiber. The measured sensitivities at 56 and 32 Gb/s are −9- and −13-dBm optical modulation amplitude, respectively. [ABSTRACT FROM AUTHOR]

We report a dc-coupled burst-mode (BM) receiver for optical links in a dynamically reconfigurable network. Through the introduction of interlocking search algorithms, a robust 25 Gb/s BM operation is achieved with 31 ns lock time. At the beginning of the burst, the receiver first performs input dc current offset calibration in 12.5 ns, then achieves phase lock in 18.5 ns, and after that tracks data using a phase interpolator (PI) based bang-bang clock and data recovery (CDR). The sensitivity of the receiver is -10.9\;\text dBm (average power, \text BER < 10^-12) at 25 Gb/s, tested with a single mode 1550 nm reference optical transmitter. There is no significant sensitivity penalty in the presence of \pm 100\;\text ppm frequency offset between the transmitter and the receiver. Measured power efficiency of the receiver at 25 Gb/s is 4.4 pJ/bit. The core of the 32 nm SOI CMOS circuit occupies 200\; \upmu\text m \times 300\;\upmu \text m. [ABSTRACT FROM PUBLISHER]

We report error free ( \textrm BER<10^-12 ) operation of a directly non-return-to-zero modulated 850-nm vertical cavity surface-emitting laser (VCSEL) link operating to 71 Gb/s. This is the highest error free modulation rate for a directly modulated laser of any type. The optical link consists of a 130-nm BiCMOS driver IC with two-tap feed-forward equalization, a wide bandwidth 850-nm VCSEL, a surface illuminated GaAs PIN photodiode, and a 130-nm BiCMOS receiver IC. [ABSTRACT FROM PUBLISHER]

We report three 850 nm, vertical-cavity surface-emitting laser (VCSEL)-based optical links using 90 nm complementary metal-oxide-semiconductor (CMOS) circuits that achieve new records in speed and power efficiency. Two receiver (RX) circuit designs explore the tradeoffs between speed, power, and silicon area. The two RXs are first tested with a simple transmitter (TX), delivering full-link power efficiencies of 1.37 pJ/bit at 15 Gb/s and 3.6 pJ/bit at 25 Gb/s. An improved TX using feed-forward equalization (FFE) and an advanced VCSEL is then introduced. The link using the FFE TX achieves full-link power efficiencies of 1.5, 2.0, and 3.8 pJ/bit at 22.5, 25, and 28.5 Gb/s, respectively. [ABSTRACT FROM PUBLISHER]