1. Performance Enhancement of PFET Planar Devices by Plasma Immersion Ion Implantation (P3I).
- Author
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Ortolland, Claude, Horiguchi, Naoto, Kerner, Christoph, Chiarella, Thomas, Eyben, Pierre, Everaert, Jean-Luc, del Agua Borniquel, Jose Ignacio, Poon, Tze, Santhanam, Kartik, Porshnev, Peter, Foad, Majeed, Schreutelkamp, Robert, Absil, Philippe, Vandervorst, Wilfried, Felch, Susan, and Hoffmann, Thomas
- Subjects
ION implantation ,ION bombardment ,SEMICONDUCTOR doping ,ELECTRODES ,DOPED semiconductors ,PLASMA gases - Abstract
A study of doping the pMOS Lightly Doped Drain (LDD) by Plasma Immersion Ion Implantation (P3i) with BF3 is presented which demonstrates a better transistor performance compared to standard beam line Ion Implantation (I/I). The benefit of P3i comes from the broad angular distribution of the impinging ions thereby doping the poly-silicon gate sidewall as well. Gate capacitance of short channel devices has been measured and clearly shows this improvement. This model is clearly supported by high resolution 2D-carrier profiles using Scanning Spreading Resistance Microscopy (SSRM) which shows this gate sidewall doping. The broad angular distribution also implies a smaller directional sensitivity (to for instance the detailed gate edge shape) and leads to devices which are perfectly balanced, when Source and Drain electrode are switched. [ABSTRACT FROM AUTHOR]
- Published
- 2008
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