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Summary: The widespread use of Internet of Things devices has increased the demand for lower cost and more efficient lightweight ciphers. However, there is a difficult trade‐off between cost and efficiency for lightweight block ciphers. The optimizations of area and throughput are important for some constrained environments. This paper proposes two novel hardware architectures for the LILLIPUT cipher. In the novel low area structure, a new permutation layer is provided for LILLIPUT. The relationship between encryption algorithm and key scheduling algorithm is utilized to achieve optimal sharing among components, which significantly reduces hardware area. The experimental results show that the number of XOR gates and S‐boxes required for low area optimization is reduced by 52 and 8, respectively. The total area is reduced by about 18%. For high throughput structure, this paper provides 2‐round, 5‐round, and 15‐round loop unrolling designs for LILLIPUT to improve throughput. The experimental results show that the throughput of the 5‐round loop unrolling structure reaches a good level, which is relatively the most cost‐effective. In practical application, ciphers can be unrolled implementations according to the needs of devices to improve the execution speed, which can greatly reduce the execution time and complexity of the algorithm. [ABSTRACT FROM AUTHOR]

The data security of CAN bus system is receiving increasing attention with the rapid development of Internet of Vehicles (IoV). However, traditional ciphers are not the best choice due to the limitations of computation, real-time, and resources of Electronic Control Units in vehicles. Thus, this paper proposes a lightweight block cipher IoVCipher to protect the security of IoV. It is designed focus on the latency and area in round-based architectures (both encryption and decryption) to meet this resource-constrained environments. For this purpose, two S-boxes with low latency and tiny area are constructed in this paper, one involution and one non-involution. Considering the decryption latency, a low latency subkey generation method is designed. In addition, this paper proposes a new extended MISTY structure that makes the encryption and decryption of hardware implementations similar. In comparison to other low-latency lightweight block ciphers such as PRINCE, QARMA, MANTIS and LLLWBC, IoVCipher achieves an effective balance between latency and area in the round-based architecture, and IoVCipher has low latency, low area, and low energy in the fully unrolled architecture. Finally, IoVCipher is implemented on a real-time speed acquisition and encryption testbed to simulate encrypted transmission of real-time speed in a CAN bus environment. [ABSTRACT FROM AUTHOR]

Lightweight block ciphers are important for implementing security services on constrained devices today. In this paper, we propose a novel ultra-lightweight block cipher DULBC based on a dynamic SPN structure. The round function of DULBC adopts an unfixed F-function and a bit-based permutation. The choice of the F-function depends on 2 bits of the round keys. This means the encryption process of the cipher is uncertain and its security is greatly improved. Also, a strong 4 × 4 S-box with fewer logic gates is proposed, which costs low hardware resources and ensures excellent performances. We have conducted FPGA implementation and ASIC implementation on DULBC. The throughput of DULBC-80/128 is 555.03/443.84 Mbps and the area of the 16-bit serial architecture of DULBC-80/128 is 1075/1351 GEs, respectively. DULBC is secure and efficient according to our experiments and comparisons. • A novel lightweight block cipher with dynamic structure to improve security and privacy. • Performance of the 4 × 4 S-box with fewer logic gates is even better compared with the isomorphic S-boxes. • High throughput and low area consumption in hardware implementation. [ABSTRACT FROM AUTHOR]