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The drag suppression for a high-amplitude oscillating cylinder is simulated using various configurations of detached-splitter plates. Governing parameters are the length of splitters ( L ), the cylinder–splitter gap ( G ), the amplitude ( A ), and the frequency of oscillation ( f 0 ). The control-volume technique along with the ACMI (arbitrary coupled mesh interface) boundary treatment and dynamic mesh technique are used to capture the high-amplitude boundary movement. It is found that in comparison to the dynamic mesh technique, the ACMI boundary condition is more efficient for highly deforming boundaries between two adjacent domains. Furthermore, it is found that the case with double upstream splitter has the most drag reduction. The lock-on and unlocked regions for a cylinder with diameter of D are identified for dimensionless amplitudes of A / D = 0.25 and A / D = 0.5 , and the minimum values of drag coefficient for various magnitudes of dimensionless gap ( G / D ) are found. Also, the locked and unlocked configurations play an important role in the drag reduction mechanism. It is concluded that the maximum drop in the drag force occurs for the lock-on condition at dimensionless oscillation frequency of F =1.1. It is concluded that the gap size and the plate length are the least and the most effective quantities, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a newly developed smoothed-particle hydrodynamics (SPH) method for the solution of one-dimensional heat conduction problem within a nanoscale thin slab for Knudsen numbers of 0.1 and 1 under the effect of Dual-Phase-Lag (DPL) model. A novel temperature-jump boundary condition is applied to the Lagrangian particle-based mesh-free SPH method in order to take into account the boundary phonon scattering phenomenon in the micro- and nano-scales. The formulation and discretization of the non-Fourier DPL heat conduction equation containing a third-order combined spatial-time derivative together with a temperature-jump boundary condition are presented and then a proper nanoscale time-stepping of the SPH method has been introduced. The dimensionless temperature and heat flux distributions have shown a good agreement with the existing numerical and analytical data for different dimensionless times, temperature to heat flux phase-lag ratios, and the Knudsen numbers. It is found that the developed SPH method have accurately simulated the complex behavior of the DPL model with relatively low computational cost. [ABSTRACT FROM AUTHOR]

This paper investigates electrothermal aspects of high-k material as well as silicon-on-insulator (SoI) technology in the nanoscale nMOSFET by the numerical simulation of dual-phase-lag (DPL) heat conduction model under the effect of self-heating phenomenon. Three types of MOS devices including bulk, SoI, and high-k MOSFETs are considered. All of the electrothermal parameters are considered temperature-dependent, and three solution schemes including drift-diffusion (DD), hydrodynamic models, and the Monte Carlo method are compared. Consequently, the DPL-DD model is detected suitable to model the device with 100-nm gate length and \({\rm Kn}=3\) . The reason lies in low computational cost and high ability of the DPL–DD model to combine the advantages of the DPL-based thermal equation with the semiconductor equations to model the nanoscale phonon transport in the transistor. The temperature-jump boundary condition is applied on all boundaries to consider the boundary phonon scattering phenomenon. The output characteristics along with the temperature field are presented, and the effect of using high-k material on the electrothermal behavior of the transistor has been investigated. It is found that by changing the high-k gate dielectric material, the hotspot temperature decreases, and consequently, the thermal performance of the device increases. [ABSTRACT FROM PUBLISHER]

Abstract: This paper investigates the numerical simulation of non-Fourier transient heat transfer in a two-dimensional sub-100nm metal-oxide-semiconductor field-effect transistor (MOSFET). The dual-phase-lag (DPL) model with a specific normalization procedure is introduced for the modeling of nanoscale heat transport. The boundary conditions are selected similar to what existed in a real MOSFET device, both uniform and non-uniform heat generations within the transistor are applied, and the end parts of the top boundary which are in contact with the metallic material are left open. A temperature-jump boundary condition is used on all boundaries in order to consider the boundary phonon scattering at micro and nanoscale. A three-level finite difference scheme has been employed to generate the numerical results which are illustrated for a silicon sub-100nm MOSFET corresponding to the Knudsen number of 10. The results are presented at real times less than 50ps to avoid the three-dimensional effects. It is concluded that the combination of the DPL model with mixed-type temperature boundary condition is able to predict the heat flux and temperature distribution obtained from the Boltzmann transport equation (BTE) more accurate than the ballistic-diffusive equations (BDE). After verification of our results, the thermal field and the hotspot temperature within the bulk silicon are presented and the effect of adding a layer of silicon-dioxide to the transistor on its thermal behavior has been investigated. [Copyright &y& Elsevier]

Due to the importance of the transistors in nano-electronics technology, the accurate study of these nano-devices is an essential field of research. Taking into account the non-Fourier nature of heat transfer with considering the three-dimensional structure of the silicon nano-devices, are the challenges in transistor analysis which have not been studied precisely yet. Using the Monte-Carlo method for solving the Boltzmann equation, two actual three-dimensional silicon transistors are accurately simulated. First, the accuracy of the method is verified by the investigation of heat transport in different regimes for a cuboid. Then, the procedure is used to simulate a 2-D silicon nano-device. The obtained results present good consistency with the existent data. Then, the 3-D silicon structure is investigated in two different cases with various boundary conditions, and the formation of the hot zone is announced. Farther, it is attained that a temperature-jump occurs around the time t = 22 p s . This phenomena is attributed to the change of the type of the dominant heat carriers from acoustic phonons to the optical ones. Furthermore, it is found that although the transistor is still heated the peak temperature starts to decrease when time passes t = 200 p s . Moreover, as the heat source is switched off at t = 500 p s , the temperature is acquired to suffer many fluctuations until the expecting descending behaviour appears at t = 726 p s . Such deportment takes place due to the imprisoning the existent heat in the hot-spot between the isolated boundaries. Besides, the results reveals that redesigning the transistors in case two by leaving the end parts of the top boundary which are in contact with the metallic material open, strengthens the presence of the hot-spot while fastening the heat release to the environment. Also the temperature profiles of the second case exhibits odd behaviours as well. Finally, it should be emphasized that this research compensates the lack of heat transfer data for the thermal investigation of 3-D MOS devices. [ABSTRACT FROM AUTHOR]