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An analytical model for a novel triple reduced surface field (RESURF) lateral double-diffused metal–oxide–semiconductor (LDMOS) field-effect transistor with a low on-resistance n-type top (N-top) layer is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF LDMOS is presented by solving the 2-D Poisson’s equation, which can also be applied in single, double, and conventional triple RESURF structures. The vertical and lateral breakdown voltages are formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of the N-top layer ( Q\textrm {ntop} ) is derived which can give a guidance for the dose of N-top layer. The triple RESURF LDMOS with a low on-resistance N-top layer is designed and manufactured according to the analytical model. All the analytical results can be well verified by numerical and measured results, showing the validity of the presented model. [ABSTRACT FROM AUTHOR]

A novel triple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) with partial linear variable doping (LVD) N-type top (N-top) layer is proposed in this paper. Compared with the conventional triple RESURF LDMOS, a partial LVD N-top layer is introduced in the surface of N-well, providing a low on-resistance conduction path and leading to an optimized surface electric field, which alleviates the inherent tradeoff between the breakdown voltage (BV) and specific on-resistance ( R on , sp ). With the n-drift region length of 70 μm, the novel triple RESURF LDMOS obtains a high BV of 847 V and a low R on , sp of 79 mΩ cm 2 which are 76 V higher and 46 mΩ cm 2 lower than those of the conventional triple RESURF LDMOS. Therefore, the novel triple RESURF LDMOS can greatly improve the tradeoff between BV and R on , sp . Furthermore, compared with the other existing technologies in the high BV level, the novel triple RESURF LDMOS can achieve a highest figure of merit (FOM, defined as BV 2 / R on , sp ) of 9.08 MW/cm 2 and the conventional RESURF silicon limits are broken. [ABSTRACT FROM AUTHOR]

A 700 V dual-buried-layer n-channel lateral double-diffused MOSFET (DB-nLDMOS) based on substrate termination technology (STT) is presented and experimentally demonstrated in this paper. The termination region is well analyzed and designed to avoid the premature avalanche breakdown caused by the curved junction. The 2-D and 3-D numerical simulations have been performed to optimize the three key parameters of \Delta L1,\Delta L2, and \Delta L3 which impact on breakdown voltage (BV) greatly in the termination region. The simulation results show that the electric field peak is reduced and premature avalanche breakdown is avoided at the curved abrupt p-well/n-well junction with the STT. The experimental results demonstrate that low $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}} of 105.6 \textm\Omega \cdot \mathrm cm^2 based on Ld and high BV of 788 V are achieved by the DB-nLDMOS. [ABSTRACT FROM PUBLISHER]