Search

This work presents a 25 MHz adaptive on/off-time-controlled three-level buck converter with a fast reference tracking speed and high light load efficiency. The self-balancing scheme of the flying capacitor voltage is revised and extended for a broad conversion ratio range from 0.17 to 0.833. To reduce the error of the self-balancing scheme when applied to a high frequency three-level buck converter with an on-chip flying capacitor, a real-time calibration loop on the flying capacitor voltage is introduced, effectively reducing the balancing error from 340 mV to 20 mV. A turning-point output voltage prediction for the three-level buck converter is presented to achieve near-optimal reference tracking with a fast tracking speed and negligible output voltage undershoot or overshoot. The up- and down-tracking takes 81 ns and 72 ns, respectively, for a 1-V step with an inductor of 47 nH and an output capacitor of 47 nF. The three-level converter achieves a precise discontinuous conduction mode (DCM) operation with an adaptive switching frequency at light load by means of a feedback loop-based method. An approximately 28.2% increment in efficiency is achieved with a load of 10 mA. The three-level buck converter has a peak efficiency of 92.8% and an over 85% efficiency in most of the operation regions. [ABSTRACT FROM AUTHOR]

This paper presents a turning-point output voltage (TPOV) prediction method to enhance the reference tracking speed of buck converters for dynamic voltage and frequency scaling (DVFS) application. The optimal reference tracking is modeled, and the TPOV is formulated. The parasitic effects are compensated with the proposed calibration scheme. Reference tracking considering load current changes is evaluated with the proposed end-point determination method. Additionally, this work optimizes the feedback network for smooth loop transition, and incorporates the frequency-locking circuit and the error correction path to address the shortcomings of the hysteretic control. The prototype is fabricated in a 0.13- $\mu \text{m}$ CMOS process with a 1.2-V supply voltage. The converter achieves a near-optimum reference tracking over a wide range of output voltages, from 0.5 to 1 V. Various output voltage steps are measured for different load cases. For a 0.5–1-V output voltage step, with a 90-nH inductor and a 1- $\mu \text{F}$ output capacitor, the up- and down-tracking take 558 and 542 ns, respectively, matching the theoretical result of 533 ns. The prototype achieves a peak efficiency of 93.5%, and over 85% efficiency is measured with $\mathrm {V}_{\mathrm {O}}$ from 0.5 to 1 V and $\mathrm {I}_{\mathrm {O}}$ from 130 to 550 mA. [ABSTRACT FROM AUTHOR]

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]