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This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

A 2.5-GHz clock recovery (CR) unit is proposed within an efficient 2.5-Gb/s ultrawideband (UWB) transceiver fabricated in 28-nm FDSOI for low-power chip-to-chip communications over short distances. The CR circuit is made of two complementary phase-locked loops (PLLs), one for fast frequency locking and the other for high-bandwidth phase tracking. Forward body-biasing (FBB) is used to control a back-bias-controlled oscillator (BBCO) and recover a 2.5-GHz clock frequency. This feature allows to reduce both the supply voltage and the power consumption, while preserving the CR functionality over a wide range of process-voltage-temperature (PVT) variations, including skewed process corners. The CR occupies a silicon area of 0.043 mm2, locks in less than $1.1~\mu \text{s}$ , generates an RMS long-term jitter of 6.5 ps, and consumes 1.034 mW while in-lock. This results in an energy value of 0.414 pJ/cycle and a jitter FoM of −224 dB.

International audience; In this article, a 3D electro-optical simulation method is presented in order to estimate the Photon Detection Probability (PDP) of Single-Photon Avalanche Diodes (SPAD). The efficiency of the proposed simulation flow is demonstrated through a complete study aimed at improving the PDP of a SPAD implemented in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology using a light-trapping approach (thanks to the patterning of Shallow Trench Insolation-STI layer). Simulation shows an increase of PDP spectrum of over 50% at wavelengths of 400-550nm and 750-1000nm and of 10-15% at the wavelengths of 550-750nm, compared to a reference SPAD without any nanostructuration.

A 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 25.3 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25% duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.

This keynote is describing the evolution of Artificial Intelligence (AI) adoption to the Edge for maximizing Data processing at the User experience level to treat as much as possible data analysis without saturating Internet traffic and Cloud data centers. Evolution of Neural Network (NN) computing through progressive usage of In Memory Computing (IMC) is also described. A few examples of Artificial Intelligence at the Edge are also commented. We then describe how at ST, we address competitive solutions for Edge AI thanks to differentiated FD-SOI CMOS technology, Phase Change Memory (PCM) embedded memory integration and advanced NN and IMC design solutions.

This article presents a study of Single Photon Avalanche Diodes (SPAD) implemented in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology based on transient TCAD simulations. The integration of SPAD in this technology is currently being studied. This work allows for a better understanding of the mechanism behind the quite high Dark Count Rate (DCR) measured at relative low excess bias voltages with the previous FD-SOI SPAD design. In this study, TCAD transient simulation methodology is introduced to better understand SPAD behavior during the avalanche process. TCAD simulations revealed that Shallow Trench Isolation (STI) structures in the active area have a negative effect on avalanche quenching, because of slower carrier evacuation with possible occurrence of secondary avalanches in series. Based on this analysis, we propose a new SPAD architecture to achieve a lower DCR.

This article proposes a 3D electro-optical simulation method to estimate the Photon Detection Probability (PDP) of Single-Photon Avalanche Diodes (SPAD) implemented in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology. In order to improve the PDP of SPAD implemented in FD-SOI CMOS technology, a light-trapping approach is studied, thanks to the patterning of Shallow Trench Insolation (STI) layer and the patterning of Silicon substrate, respectively in the case of Front Side Illumination (FSI) and Back Side Illumination (BSI). An average gain of 50% for wavelengths between 400nm-1000nm and of 200% for wavelengths between 800-1000nm respectively in the case of FSI and BSI are achieved. Based on this study, IC fabrication including several designs of SPAD implemented in FD-SOI CMOS technology with different pattern sizes is launched for future electro-optical characterization.

A low-phase-noise injection-locked oscillator (ILO) based on a cross-coupled oscillator topology is presented. The prototype ILO was designed and fabricated in a 65-nm Partially Depleted SOI (PD-SOI) CMOS technology from STMicroelectronics. The 27.47 GHz free-running oscillator exhibits a phase noise of –119.23 dBc/Hz at 10-MHz offset, and its robustness to process variations is less than 4 dB. Using a common mode injection, the proposed ILO generates an output frequency at 27.5-GHz when the oscillator is injection-locked by the 5th harmonic of a 5.5 GHz reference. In injection-locked mode, the phase noise performance is then –116.75 dBc/Hz and – 135 dBc/Hz at 1-MHz and 10-MHz offsets, respectively, while solely consuming 2.06 mW from a 1 V supply. The total active area is 0.031 mm2 (excluding I/O pads).

This paper proposes a 16MB e-NVM macrocell for automotive grade 0 microcontroller based on a PCM cell with a Bipolar Transistor (BJT) selector. The solution is developed in proprietary 28nm FD-SOI CMOS technology, with a Super-STI scheme that has enabled high dense e-NVM with 0.019µm2 cell size [1]. Macrocell organization offers the capability to be configured by application either for Over-The-Air (OTA) mode up to 24MB, or for 16MB extra reliability mode, with two cells per bit, still resulting in an extremely competitive equivalent bit-cell size (0.038µm2). Cell Mode configuration can be dynamically tuned, with a unique set of features for flexible assisted OTA software update. The integration of a 16MB PCM cell array, extensible up to 24MB, in an automotive grade product-like test vehicle chip is presented here as the evolution of the first Embedded PCM macrocell for automotive [2], complementing, the fulfillment of all criteria in the demanding automotive environment [3] [4].

International audience; In order to improve amplifiers’ power gain for a close to fmax operation, a methodology to size the embedding of any active two port is described and then applied to the design of a single-stage amplifier as a proof of concept. The 184 GHz measured 28 nm FD-SOI CMOS amplifier presents a power gain of 7.6 dB, a bandwidth of 20 GHz, a Psat of -3.7 dBm and a peak PAE of 4.2 % for a power consumption of 5.1 mW.

Handheld microwave thermoacoustic imaging (TA) can be used to image subcutaneous vasculature for biometric authentication and to monitor blood-vessel health, but the system requires a compact silicon microwave power amplifier (PA) with peak output power on the order of 10 W to be portable, affordable, and ubiquitous. This work presents a 55nm BiCMOS 4.9 GHz PA with 37.3 dBm peak output power that operates at a pulse width of 50 ns - $2\ \mu\mathrm{s}$ for a duty cycle of 0.025 - 1%. The PA serves as the transmitter in a microwave TA system, which generates the first known TA images of tissue phantoms using a compact transmitter built on a silicon substrate.

A compact, fully-integrated 196GHz FSK transmitter for point-to-point wireless communication is prototyped with a 55nm SiGe BiCMOS process, demonstrating a single-channel data rate of 10Gb/s with a chip area of 0.68mm2. The achieved single-channel data rate is around 5x higher compared with all other FSK wireless transmitters and the chip area is around 4x smaller compared with other state-of-the-art sub-THz wireless transmitters. Unlike conventional FSK transmitters which encode data with two oscillators at different frequencies or with the control voltage of varactors in the LC tank, the proposed FSK transmitter performs data modulation by varying the phase shift of tunable phase shifting couplers in a coupled oscillator loop, resolving the issues of extra power consumption and long frequency settling time. In theory, frequency shift based on this mechanism is instantaneous without overshoot/undershoot issues.

The adoption of 5G standards requires new wireless devices to support not only traditional RF bands, but also mmW frequencies up to and beyond 40GHz. Such mmW hardware typically requires narrowband LC resonant circuits for efficient, low-noise operation. For widely-tuned software-defined systems, multi-octave LC tuning is not achievable due to the lack of a practical, solid-state tunable inductive element, limiting the mmW performance of software-defined radios. In this paper, we present a novel, compact, lumped/distributed LC-equivalent resonator capable of continuous tuning over more than four octaves in frequency while maintaining a practical quality factor in an unmodified 28nm FDSOI CMOS for the first time. This resonator is used to implement a cross-coupled LC VCO tunable from 3.1 to beyond 51GHz requiring less than 0.208mm2 of area, less than 8mW of power, and achieving a state of the art peak FOM T for multi-octave tunable mmW VCOs of −198.2dBc/Hz.

International audience; In the context of autonomous keyword spotting and sound detection, this paper proposes a low power feature extraction unit generating spectrograms that represent a unique signature allowing the classification of audio signals. This system is composed of a continuous-Time digital signal processing feature extractor combined with a convolutional neural network engine. The study evaluates the hardware requirements to implement the feature extraction unit using an advanced CMOS process. Furthermore, a simulation of the complete system using Matlab® reveals that the recognition accuracy remains higher than 90% while offering a power consumption 4000X lower than a conventional discrete time system.

This paper presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115–135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB were measured. A data rate of 36 Gb/s was wirelessly measured at 30-cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error rate (BER) of 1e-6. The measured receiver sensitivity at this BER is −41.28 dBm. The prototype occupies 2.5 $\times $ 3.5 mm2 of die area, including PADs and test circuits (2.5-mm2 active area), and consumes a total dc power of 200.25 mW.

Terahertz (THz) sources with stabilized output frequencies are desired in many systems, however, the design of conventional THz phase-locked loops encounters many challenges. In this paper, a fully on-chip frequency-stabilization feedback mechanism is proposed, which avoids the use of both frequency dividers and the off-chip reference, achieving much lower power consumption and system integration cost. Using this scheme, two circuit prototypes are designed in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology. The first one is a 302–332-GHz frequency-stabilized source with ultralow power consumption. It achieves a −13.9-dBm probed output power with a dc power consumption of only 51.7 mW. The second design is a 308–317-GHz frequency-stabilized high-output-power radiating array, which achieves a peak-radiated power and EIRP of 4.6 mW and 24.7 dBm, respectively, with a total dc power consumption of 1.18 W. With significantly lower system integration cost and power consumption, the proposed scheme is attractive for many applications that require short coherence time, such as THz active imaging systems and short-range millimeter-wave (mm-wave)/THz FMCW radars. With further calibration and enhancement in long-term stability, this scheme will also be useful in systems like communication transceivers.

Terahertz (THz) radiation ranging from 300 GHz to 10 THz [1] has attracted a growing number of researchers over the past decade. They are enthusiastic about its great potential for biomedical diagnoses, security screening, and highspeed communication. For instance, a THz wave can propagate through dry, nonmetallic, and nonpolar materials with small attenuation. This ability, combined with its small wavelength (versus microwave) and photon energy (versus X-ray), makes a THz wave an ideal option for nonionizing medicalimaging, such as a burn injury assessment [2] or skin cancer diagnosis [3]. A short-range wireless link operating at such an unallocated band is also expected to significantly boost transmission speeds. In [4], a 25-Gb/s link with a 220-GHz carrier was demonstrated over a distance of 50 cm. A higher data rate of 100 Gb/s is anticipated in the near future [5].

This work presents a fully integrated energy efficient wireless transmitter (TX) at 220GHz. The transmitter employs on-off keying (OOK) scheme for the modulation of the baseband data. The measurements demonstrate 20Gbps data-rate with 63mW of DC power consumption including CMOS buffer. The chip is fabricated in 55nm SiGe BiCMOS process and occupies 0.38mm2 in area.

We have seen an emergence of quantum-computing activity in recent years from an uptick of startups to investments at established companies. Yet, there is more to quantum systems than simply computing. In fact, quantum systems by themselves do not work, and classical electronics are needed to interface with quantum devices. In this forum, we look at electronics, in particular CMOS electronics, for use in combination with quantum devices from the designer’s perspective. We explore these systems from specifications to testing, often at cryogenic temperatures, and discuss recent successes and future trends.

The increasing demands for compact, low-cost, and high-resolution radar systems have pushed the operation frequency to the terahertz range due to the shorter wavelength and larger available bandwidth [1–5]. However, the best-reported range resolution cannot go below 1.5mm with a 100GHz bandwidth [1], which is not enough for many industrial applications like small-defect detection and surface screening. Moreover, most previous works [3–5] are based on conventional transceiver architectures that use separate antennas for TX and RX or use parallel multi-antenna designs to increase the frequency bandwidth [1]. These structures not only increase the chip size but also degrade the radar performance when they are placed at the focal point of a collimating lens. This degradation occurs due to the separated antenna phase centers, which are not well located at the collimating lens focal point, causing a multi-beam radiation pattern. To overcome these challenges, we have adopted an autodyne FMCW radar structure [6, 7] with a phase processing method on the radar IF signal [7]. The autodyne is an oscillator that simultaneously carries out functions of generating the transmission and mixing the transmitted and reflected signals. There is no separate path for the RX signal in the autodyne, as the radiated and reflected signals exist at the same point of the autodyne circuit. Hence, it utilizes a combined antenna with a single-phase center for both transmitting and receiving parts. Besides, the phase processing method allows us to measure short ranges with an error no more than one-tenth of one-percent, which in terahertz frequencies provides micrometer resolutions [7]. Using these approaches, this paper demonstrates an autodyne FMCW radar with 66.7GHz bandwidth from 191GHz to 257.7GHz with a minimum range resolution of $54 \mu \mathrm{m}$. Across state-of-the-art, this design improves the range resolution by 28 times.

COVID-19 resulted in massive human casualties and an economic collapse across the globe. To prepare for the future, this Forum introduces the key challenges with detection and prevention of pandemics and highlights some potential opportunities for employing silicon technologies to quickly diagnose, treat, and prevent diseases. IC technologies that enable point-of-care diagnostics, continuous health monitoring, and lab-on-chip RNA detection continue to revolutionize healthcare. Further, high-performance computing (HPC) accelerates drug discovery, vaccine development, as well as real-time tracking of the spread of diseases and their socio-economic impacts. This Forum will address a wide spectrum of topics at the intersection of circuit/system design and bio-engineering.

The first Active Quenching - Active Reset (AQAR) circuit for a novel inherent 3D SPAD pixel is designed in a 28 nm CMOS Fully Depleted Silicon On Insulator (FDSOI) technology. Thanks to an ultra-fast detection circuit, the avalanche is detected in less than 50 ps and quenched in 200 ps. Thanks to this fast detection and active quenching, the avalanche charge in the Space Charge Region (SCR) is reduced by 50 % which should result in a 50 % afterpulsing reduction. With the proposed pixel, the fill factor is no longer limited by the associated circuitry.

International audience; The Switched-Capacitor Power Amplifier (SCPA) has become a key enabler for modern wireless communication because of its high efficiency, high linearity, and high integrability. This paper discusses the impact of the extended Forward Body-Biasing (FBB) feature in 28 nm FD-SOI technology on Ultra-Low Voltage (ULV) SCPA. A new model of the Drain Efficiency (DE) and System Efficiency (SE) including body-biasing and drivers power consumption is introduced and validated with SpectreRF simulations. FBB on the SCPA improves by up to 14 % and 67 % the SE and transistors area, respectively, compared to a nominally body-biased SCPA under 0.5 V supply voltage at 2.4 GHz, while improving linearity and enhancing PVT variations.

Sharing a common clock signal among the nodes is crucial for communication in synchronized networks. This work presents a heartbeat-based synchronization scheme for body-worn nodes. The principles of this coordination technique combined with a puncture-based communication method are introduced. Theoretical models of the hardware blocks are presented, outlining the impact of their specifications on the system. Moreover, we evaluate the synchronization efficiency in simulation and compare with a duty-cycled receiver topology. Improvement in power consumption of at least 26% and tight latency control are highlighted at no cost on the channel availability., Comment: Accepted as conference paper at IEEE ISCAS 2020

International audience; Wireless Body Area Networks (WBANs) are a fast-growing field fueled by the number of wearable devices developed for countless applications appearing on the market. To enable communication between a variety of those devices, the IEEE 802.15.6 standard was established. However, this standard has some intrinsic limitations in addressing the heterogeneity of the network nodes in terms of activity, data rates (from less than bit/s to multiple Mbit/s), energy availability, form factor, and location on, around or inside the body. To address these concerns, an alternative model is proposed that could serve as an extension of the IEEE 802.15.6 Standard. At its core is an adaptive and low-overhead synchronization scheme based on heartbeat sensing. This forms the base for a TDMA-based (Time Division Multiple Access) Media Access Control (MAC) protocol dedicated to multi-tier networks. While this effort focuses specifically on Capacitive Body-Coupled Communication (C-BCC), other physical layers can be easily incorporated as well. Based on these premises, this paper compares various random-access slot allocation approaches to accommodate the multiple data rates matching the system requirements, while incorporating a duty-cycling strategy anchored by heartbeat detection. This work proposes a novel, flexible, and robust solution, making use of heartbeat synchronization and addressing the corresponding challenges. It efficiently interconnects multiple device types over a wide range of data rates and targets a mesh of stars topology. At the cost of an increased communication latency, the proposed protocol outperforms the IEEE 802.15.4 MAC standard in terms of energy efficiency by a factor of at least 12x in a realistic scenario.

In this chapter, a 31 GHz reconfigurable balanced 2-stage power amplifier (PA) integrated in 28 nm FD-SOI CMOS technology is demonstrated aiming for SoC implementation. Fine grain wide range power gain control with more than 10 dB tuning range is enabled by body-biasing feature while the design improves VSWR robustness, stability, and reverse isolation by using optimized 90∘ hybrid couplers and capacitive neutralization over both stages. Maximum power gain of 32.6 dB, PAE_max of 25.5%, and Psat of 17.9 dBm are measured, while robustness to industrial temperature range and process spread is demonstrated. This PA exhibits a maximum ITRS figure of merit of 26,925 which is the highest reported around 30 GHz to authors’ knowledge.

Improving the energy efficiency of processor systems-on-chip (SoCs) is key to improving their performance and utility. The FD-SOI silicon process enables integrated systems that can deliver dramatic improvements in energy efficiency through system integration. This chapter presents the Raven-3 and Raven-4 testchips, fully integrated and fully featured SoCs which achieve energy-efficient operation with low overhead. RISC-V processors allow for innovation and experimentation in the context of a free, open architecture. Integrated switched-capacitor voltage regulators can achieve high conversion efficiency when coupled with adaptive clock generators. Custom SRAM macros operate at low supply voltages, enabling wide voltage scaling. An integrated body-bias generator allows run-time tuning of threshold voltage for improved performance or reduced leakage. Taken together, these innovations showcase the possibilities of FD-SOI technology.

In this letter, a novel indirect avalanche event detection is proposed and demonstrated for Single Photon Avalanche Diodes (SPADs) implemented in CMOS 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology. This approach is based on the capacitive coupling between the P-well, i.e. SPAD anode, and the transistor channel, separated by the ultra-thin buried oxide. The associated body-biasing effect is used to dynamically modulate the output of a simple voltage divider synchronously with the SPAD activity. A test-chip has been designed, fabricated and characterized to validate the proposed approach. This novel architecture opens the way for innovative SPAD processing circuitry implemented in 3D native CMOS FDSOI.

A 128-kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28-nm FD–SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient ON-chip charge pumps, i.e., 64 for boosting the voltages on write-bitlines and two for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A sense amplifier-less read architecture enables a reliable and high performance read operation. Measurements identify several meritorious metrics. The minimum read energy is identified as 8.4fJ/bit-access, achieved for 90-MHz operation at 0.3V. Furthermore, the minimum operating voltage is measured as 240mV, and data is retained in ultra-low voltage regime, ranging down to 0.2V. The bitcell area, implemented using standard design rules, is 0.261 $\mu \text{m}^{2}$ . The entire memory, including the digital test circuitry, occupies 0.161mm2 of chip area.

The system and transistor-level design of low-power millimeter wave (mm-wave) active tags in silicon is discussed in detail. Two active mm-wave tags with identical system architecture, padframe, and chip size were designed and fabricated in 55-nm SiGe BiCMOS and 45-nm SOI CMOS technologies, respectively. They feature a three-stage low-noise amplifier (LNA), a wake-up detector, a BPSK modulator, and two variable gain output stages, each driving a separate transmit antenna in antiphase. The wake-up detector can be used to switch OFF all the blocks except for the LNA and detector, thus further reducing power consumption. The measured performance of the SiGe and SOI chips is remarkably similar: 19- and 20-dB gain, 9- and 8-dB noise figure, and 25-/10.8-mW (active/idle) and 18-mW power consumption, respectively. The SiGe tag was flip-chip-mounted on a mini-PCB with one receive and two transmit antennas for system level functionality tests carried out over a distance of 5 m. The SiGe-tag wake-up sensitivity was verified to be −62 dBm, in excellent agreement with simulation results.

A 170-GHz fully integrated single-chip heterodyne frequency modulated continuous-wave (FMCW) imaging radar using a 130-nm SiGe BiCMOS technology ( $f_{T}/f_{\max } = 220/280$ GHz) is reported. This system demonstrates a wide bandwidth of 27.5 GHz (16.3%) at a center frequency of 168 GHz. A design methodology to maximize the tuning range of the voltage-controlled oscillator (VCO) is presented. A co-design of the VCO, coupler, and antenna is performed to minimize the chip area and the dc power consumption. The transmitter radiates a peak power of −1 dBm with a dc-to-RF efficiency of 1.42%. At the receiver side, a subharmonic mixer is used for signal down-conversion. The system achieves a measured sensitivity of 87 fW with a total dc power consumption of 67 mW. The prototype is capable of forming 2-D and 3-D images with a range resolution of 7 mm. To the best of our knowledge, this fully integrated imaging radar demonstrates the highest sensitivity and radiation efficiency among all imaging systems around 200 GHz. Moreover, the system is capable of practical 2-D and 3-D imaging with significantly lower dc power consumption compared to the state-of-the-art FMCW radars.

Wireless communication using terahertz/sub-terahertz band can alleviate the spectrum scarcity in conventional RF ands and satisfy the drastically expanding demands for capacity. In this paper, a spatial-orthogonal ASK transmitter architecture is presented. The self-sustaining oscillator-based transmitter architecture has an ultra-compact size and excellent power efficiency. With the proposed high-speed constant-load switch, significantly reduced modulation loss is achieved. Using polarization diversity and multi-level modulation, the throughput is largely enhanced. Array configuration is also adopted to enhance the link budget for higher signal quality and longer communication range. Fabricated in a 130-nm SiGe BiCMOS technology, the transmitter achieves an EIRP of 21 dBm and dc-to-THz-radiation efficiency of 0.7% in each spatial channel. A 24.4-Gb/s total data rate over a 10-cm communication range is demonstrated. With an external Teflon lens system, the demonstrated communication range is further extended to 52 cm. Compared with prior art, the proposed transmitter shows much higher power efficiency.

We propose a nonlinear device model and a systematic methodology to generate maximum power at any desired harmonic. The proposed power optimization technique is based on the Volterra-Wiener theory of nonlinear systems. By manipulating the device nonlinearity and optimizing the embedding network, optimum conditions for harmonic power generation are provided. Using this theory, a 920–944-GHz frequency quadrupler is designed in a 130-nm SiGe:C process. The circuit achieves the peak output power of −17.3 and −10 dBm of effective isotropic radiated power and consumes 5.7 mW of dc power. To the best of our knowledge, this circuit demonstrates the highest generated power among Si/SiGe-based sources at this frequency range.

International audience; One approach to enable wireless communication between body-worn nodes is to use capacitive body-coupled communication (CBCC). This technique, which uses capacitive electrodes as transducing elements, has previously been demonstrated at relatively low frequencies (

This article focusses on Single Photon Avalanche Diodes (SPAD) integrated in CMOS UTBB FDSOI (Ultra-Thin Body and Box Fully Depleted Silicon-On-Insulator technology), as an original approach for natively 3D SPAD pixels. In parallel to the optimization of the SPAD performances, some design issues relative to body-biasing effects are discussed in this paper. The associated electronics placed on top of the SPAD is constrained: the well layer below the box must be a P-type. Thus, only regular threshold voltage NMOS and low threshold voltage PMOS transistors can be used. The SPAD avalanche events affect the electronics through body-biasing effects, which can be advantageously exploited for an indirect sensing of the SPAD activity. Two simple indirect sensing cells are then studied. Firstly, a voltage divider realized with two transistors in series (PFET and NFET operating as active resistances) is simulated and measured to demonstrate its ability to detect avalanches. Secondly, an even simpler cell is studied, as it consists of only one NMOS transistor configured as an equivalent capacitive bridge (gate and box capacitances). Finally, the advantages and drawbacks from a design point of view are addressed.

This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 $\mu \text{m}$ by 250 $\mu \text{m}$ . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

International audience; This paper presents a single-bit RF transmitter based on single-bit switched-capacitor RF digital-to-analog converters (DACs) embedded in an finite-impulse response (FIR) filter (FIR-DACs). The transmitter system comprises a single-bit quadrature delta-sigma modulator (M), a digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete-and continuous-time filtering. The on-chip part of the FIR-DAC is built exclusively with CMOS inverters and metal-oxide-metal capacitors, which are implemented in the interconnect layers to propose a compact fully digital solution, suitable for advanced CMOS nodes. A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete-and continuous-time filtering, the out-of-band quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in a 28-nm FD-SOI CMOS technology with ten metal layers and occupies a total active area of only 0.047 mm 2. The overall power consumption is 38 mW at 4.6-dBm peak output power, 900-MHz carrier frequency, and 1-V supply. FD-SOI body bias V t tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise high-frequency I/Q interleaving, which enables high image and local oscillator rejections. The resulting power consumption, surface, and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications. Index Terms-28-nm FD-SOI, all-digital transmitter, body bias, delta-sigma modulation (M), finite-impulse response filter (FIR), finite-impulse response digital-to-analog converter (FIR-DAC), switched-capacitor (SC) DAC.

The paper proposes a BEOL PCM-based e-NVM solution integrated in a 28nm FD-SOI CMOS technology, giving excellent performances in terms of area, read and write time and temperature range. The integration of a 6MB PCM in an automotive grade (Tj up to 165C) microcontroller chip is presented here, exhibiting a robust solution satisfying all criteria of the demanding automotive environment. The Ge x Sb y Te z material used for the PCM [1] has been tuned to reach the 165C compliance and 10 years data retention. CMOS 28nm FD-SOI has been determined as the optimal technology to exploit PCM capabilities [2]. Technology also offers full feature 5V devices required for automotive application. Body bias of the FD-SOI allows controlling the quiescent leakage both in circuitry and in the unselected bits inside the memory array, optimizing the functionality.

A single-channel 115-135GHz direct demodulation RF-to-bits 8PSK RX is presented. The output of this receiver is demodulated bits, obviating the need for power-hungry high-speed-resolutions ADCs. A novel RF-correlation-based idea is introduced to enable 8PSK direct demodulation. A max conversion gain of 32dB and min NF of 10.3dB was measured. A data rate of 36Gbps was wirelessly measured at 0.3m distance and directly demodulated with a BER of $10^{-6}$. The measured receiver sensitivity at this BER is -41.28dBm.

A 320 GHz fully integrated terahertz imaging system is reported. The system is composed of a phase-locked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 130 nm SiGe BiCMOS technology ( $f_{T}/f_{\max } = $ 220/280 GHz). To enhance the imaging sensitivity, a heterodyne coherent detection scheme is utilized. To obtain frequency coherency, fully integrated phase-locked loops are implemented on both the transmitter and receiver chips. According to the measurement results, consuming a total dc power of 605 mW, the transmitter chip achieves a peak radiated power of 2 mW and a peak EIRP of 21.1 dBm. The receiver chip achieves an equivalent incoherent responsivity of more than 7.26 MV/W and a sensitivity of 70.1 pW under an integration bandwidth of 1 kHz, with a total dc power consumption of 117 mW. The achieved sensitivity with this proposed coherent imaging transceiver is around ten times better compared with other state-of-the-art incoherent imagers. To the best of our knowledge, this paper demonstrates the first fully integrated coherent terahertz imaging transceiver on silicon.

A 234–261-GHz signal source with record 7.2-dBm output power at 240 GHz and −105 dBc/Hz phase noise at 10-MHz offset is reported. Fabricated in a production 55-nm SiGe BiCMOS process with HBT ${f}_{\mathrm {T}}/{f}_{\mathrm {MAX}}$ of 330/350 GHz, the circuit includes a 120-GHz fundamental frequency VCO with 1.2-V AMOS varactors, a broadband MOS-HBT cascode LO tree driving a divide-by-128 chain, and a doubler with a record drain efficiency of 11.9%. The total power consumption of the signal source is 386 mW resulting in a DC-to-RF efficiency of 1.3%. A detailed discussion of the candidate LO-tree and doubler topologies and of the design methodology, which capitalizes on the MOS-HBT cascode and unique features of the 55-nm SiGe BiCMOS process, is provided.

A 2.4 GHz interferer-resilient wake-up receiver for ultra-low power wireless sensor nodes uses an uncertain-IF dual-conversion topology, combining a distributed multi-stage N-path filtering technique with an unlocked low-Q resonator-referred local oscillator. This structure provides narrow-band selectivity and strong immunity against interferers, while avoiding expensive external resonant components such as BAW resonators or crystals. The 65 nm CMOS receiver prototype provides a sensitivity of −97 dBm and a carrier-to-interferer ratio better than −27 dB at 5 MHz offset, for a data rate of 10 kb/s at a 10−3 bit error rate, while consuming 99 $\mu \text{W}$ from a 0.5 V voltage supply under continuous operation.

Two distributed circuits based on MOS-HBT cascodes are reported in a 55-nm SiGe BiCMOS technology and are aimed at a single-chip time-interleaved transceiver for future 1-Tb/s optical links. The first, a DC-135-GHz single-ended distributed amplifier (DA) was optimized for low noise, linear receivers, and has a measured noise figure (NF) $ 7 dB up to 88.5 GHz, 800 mVpp of linear input range, and 8.5 dB gain. Operation was confirmed with PRBS-31 eye diagram measurements up to 120 Gb/s. Additionally, a novel time-interleaved distributed power DAC test circuit was implemented as a proof-of-concept to investigate the maximum achievable output bandwidth at a differential output voltage swing of 6 Vpp, as needed to directly drive an optical modulator. Simulations of the doubly segmented 6-bit DAC show 4-PAM output eye diagrams at up to 120 GBaud. The measured clock-input-to-data-output small-signal bandwidth is 65 GHz. When the DAC is measured as a switching large-swing driver, the differential output voltage swing remains larger than $5.4~\text {V}_{\mathrm {pp}}$ beyond 50 Gb/s. Time interleaving of 4 thermometer MSBs is demonstrated experimentally to form a 1.8- $\text{V}_{\text {pp}}$ differential, 10-GBaud 3-PAM output signal. The experimental sampling rate is limited to 10 GS/s by the capacitance and bandwidth of the low-frequency probes and pads used for the data lanes.

A high-power 320 GHz transmitter using 130 nm SiGe BiCMOS technology ( $f_{T}/f_{\max} =$ 220/280 GHz) is reported. This transmitter consists of a 4 × 4 array of radiators based on coupled harmonic oscillators. By incorporating a signal filter structure called return-path gap coupler into a differential self-feeding oscillator, the proposed 320 GHz radiator simultaneously maximizes the fundamental oscillation power, harmonic generation, as well as on-chip radiation. To facilitate the TX-RX synchronization of a future terahertz (THz) heterodyne imaging chipset, a fully-integrated phase-locked loop (PLL) is also implemented in the transmitter. Such on-chip phase-locking capability is the first demonstration for all THz radiators in silicon. In the far-field measurement, the total radiated power and EIRP of the chip is 3.3 mW and 22.5 dBm, respectively. The transmitter consumes 610 mW DC power, which leads to a DC-to-THz radiation efficiency of 0.54%. To the authors' best knowledge, this work presents the highest radiated power and DC-to-THz radiation efficiency in silicon-based THz radiating sources.

While there exists a wide variety of radio frequency (RF) technologies amenable for usage in Wireless Body Area Networks (WBANs), which have been studied separately before, it is currently still unclear how their performance compares in true on-body scenarios. In this paper, a single reference on-body scenario&mdash, that is, propagation along the arm&mdash, is used to experimentally compare six distinct RF technologies (between 420 MHz and 2.4 GHz) in terms of path loss. To further quantify on-body path loss, measurements for five different on-body scenarios are presented as well. To compensate for the effect of often large path losses, two mitigation strategies to (dynamically) improve on-body links are introduced and experimentally verified: beam steering using a phased array, and usage of on-body RF repeaters. The results of this study can serve as a tool for WBAN designers to aid in the selection of the right RF frequency and technology for their application.

In this paper, a 308-317GHz radiating source is presented. The output frequency of the 6×4 radiator array is stabilized with an entirely on-chip frequency detection and feedback mechanism realized mainly by passive EM structures. This feedback mechanism eliminates the need for both frequency dividers and the off-chip reference, achieving much lower system cost and power consumption. Fabricated using a 0.13µm BiCMOS process, the proposed source achieves a peak radiated power and EIRP of 4.6mW and 24.7dBm, respectively, with a total de power consumption of 1.18W. The frequency tuning range is larger than 2.7%. The measured phase noise at IMHz offset is −80.1dBc/Hz.

The THz band has shown its unique characteristics and great potential in many applications. Harmonic oscillators are commonly used to generate THz signals; however, due to supply noise and ambient environment changes, free-running THz oscillators exhibit large spectral linewidth and frequency drift. As a result, frequency stabilization is required in many systems. Conventionally, PLLs are used for this purpose [1-3]; however, major challenges exist when frequency goes into THz band. Since the division ratio (N) is large in THz PLLs (103 to 104) and the reference phase noise is multiplied by N2 to the output, a high-quality off-chip crystal oscillator is needed to keep the noise contribution low enough. Moreover, the large N causes significant VCO-noise folding, potentially degrading the output in-band phase noise. Finally, injection-locking frequency dividers (ILFDs) in THz range provide insufficient locking range, which limits the achievable output frequency range. To boost the ILFD locking range, higher injection power or multiphase injection [1,4] is needed, which significantly increases the power consumption. In this paper, an entirely-on-chip frequency-stabilization feedback loop for mm-wave/THz sources is presented. The feedback loop eliminates the need for both frequency dividers and off-chip crystal oscillators, resulting in much lower cost and power consumption. To show the feasibility, a 301.7-to-331.8GHz source is designed in the STMicroelectronics 0.13μσι SiGe:C BiCMOS technology.

An embedded digital temperature sensor based on a single-ended probe is implemented in a 28 nm fully depleted silicon-on-insulator process. The nMOS-only ring-oscillator probe uses single-point calibration based on body-bias tuning of its well for process compensation. Nonlinearity compensation is implemented on-chip in custom digital logic, resulting in an area-efficient (225 ${\boldsymbol \mu }\text{m}^{\mathbf{2}}$ per probe, 11 482 ${\boldsymbol \mu }\text{m}^{\mathbf{2}}$ for the full system) sensor while achieving −1.4 °C/ +1.3 °C accuracy using 2.0 nJ/sample and maintaining functionality over a 0.62–1.2 V range, making it suitable for temperature monitoring in digital systems-on-chip.

This paper reports the first experimental results obtained on a Single Photon Avalanche Diode (SPAD) implemented, in a 28nm FDSOI CMOS technology. The main originality relies on the integration of the SPAD below the buried oxide with the logic on-top in the thin silicon layer, providing an intrinsic 3D stack. The expected benefits are a much higher fill factor with embedded high performance and low power electronics. A test-chip has been fabricated with the commercial STMicroelectronics CMOS28FDSOI technology without any design rule violation nor process customization. SPAD breakdown has been investigated with electroluminescence cartography and breakdown voltage measurements. Afterwards, first dark count rate measurements are reported according to temperature and excess bias. To our knowledge, it is the first demonstration of SPAD devices in a FDSOI CMOS technology. Based on these encouraging results, the study will be pursued for more statistical data acquisition and for SPAD characterization under illumination.