Search

This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure. Index Terms--Distributed modeling, high-speed, layout parasitics, power devices, silicon technology.

The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency. Index Terms--Integrated transformers, layout scaling, lumped modeling, on-wafer measurements, RF integrated circuits (ICs).

A lumped scalable model for spiral inductors in silicon bipolar technology has been developed. The effect of three different cross sections on inductor performance was first investigated by comparing experimental measurements. Using both the results of this analysis and three-dimensional electromagnetic simulation guidelines, several circular inductors were integrated on a radial patterned ground shield for model validation purposes. The model employs a novel equation for series resistance with only one fitting parameter extracted from experimental measurements. All other model elements were related to technological and geometrical data by using rigorous analytical equations. The model was validated using one- and two-port measured performance parameters of 45 integrated inductors, and excellent agreement was found for all considered geometries up to frequencies well above self-resonance. Index Terms--Bipolar technology, integrated inductors, lumped model, patterned ground shield.

The low-voltage power capabilities of a low-cost high-performance silicon bipolar process were investigated. By optimizing the emitter finger layout, epilayer thickness, and collector doping level, efficiency values up to 83% were achieved by on-wafer load-pull measurements on a single-cell test device operating at 1.8 GHz and 2.7-V power supply. The detrimental effect of the emitter distributed resistance on the current capability of long-emitter bipolar transistors was also considered. An analytical model for a proper device design was derived and experimentally validated. Using the optimized unit power device, a 1.8-GHz 2.7-V three-stage monolithic power amplifier was implemented, which provides a 57% power-added efficiency and a 33-dB gain while delivering a 34-dBm output power to the load. Index Terms--DC current capability, mobile communications, RF power amplifier (PA), silicon bipolar technology.