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Based on the InAlAs/InGaAs heterostructure doping-channel field-effect transistors (DCFETs), three co-integrated devices are demonstrated. After removing some material layers, the enhancement/depletion-mode devices and inverter logic were formed. The InAlAs/InGaAs co-integrated structures consist of an enhancement-mode device with single channel and two depletion-mode devices with double and triple channels, respectively. The insertion of an undoped large energy-gap layer between the metal gate and active channels can improve the gate breakdown voltage and turn-on voltage. Besides, by the studied integrated DCFETs two transfer characteristics are implemented for direct-coupled FET logic (DCFL) circuit applications as compared to the previous reports with only single logic transfer characteristic. Consequently, the integrated AlInAs/GaInAs DCFETs provide a promise for signal amplification and multiple inverter logic applications.

In this paper, the characteristics of InP/InGaAs abrupt, setback, and heterostructure-emitter heterojunction bipolar transistors (HBTs) are comparatively investigated by twodimensional simulation analysis. In the setback (heterostructure-emitter) HBT, a thin 50 A undoped In0.53Ga0.47As (n-In0.53Ga0.47As) layer is inserted between n-InP emitter and p+-InGaAs base layers to lower the energy band at emitter side for decreasing the collector-emitter offset voltage. The simulated results exhibits that the abrupt HBT has the largest current gain, the largest collector-emitter offset voltage, and the smallest unity gain cutoff frequency. While, the setback and heterostructure-emitter HBTs exhibit the smallest current gain and offcet voltage, respectively. Consequentially, the demonstration and comparison of the three-type HBTs provide a promise for design in circuit applications.

Based on the employments of an InGaP/GaAs superlattice emitter and a thin InGaAs pseudomorphic base structure, the device with excellent transistor action and multiple S-shaped negative-differential-resistance (NDR) switching behavior are achieved. Under normal transistor operation mode, the tunneling electrons could easily transport from InGaP/GaAs superlattice over the n-GaAs emitter layer into the thin InGaAs pseudomorphic base region for reducing the base–emitter turn-on voltage and promoting the current gain. In particular, an interesting multiple S-shaped NDR behavior is observed under inverted operation mode due to the avalanche multiplication and confinement effect for electrons at the interface between superlattice and emitter layer, respectively. As an appropriate voltage source and a load resistor are applied, three stable operation points are obtained.

In this paper, high device linearity and characteristics of an InGaP/GaAs/InGaAs camel-like gate delta-doped p-channel field-effect transistor is demonstrated. The energy band and hole distribution are depicted with respect to the device performance. Due to the npn depletion of the camel-like gate structure, the considerable conduction band discontinuities at n + -InGaP/p-GaAs and p-GaAs/i-In 0.15 Ga 0.85 As heterojunctions, and the good confinement effect for holes in InGaAs quantum well, a large gate turn-on voltage is achieved. The drain saturation current linearly increases with the gate voltage and the high device linearity is illustrated by fitting the drain current versus the gate voltage. The excellent performance of the studied device is promise for linear amplifiers and high-frequency circuit applications.

Carbon incorporation in strained-Si surface channel NMOSFET is investigated. Due to the ∼52% lattice mismatch between silicon and carbon, the channel is expected to have higher strain than strained-Si, indicating that the carrier mobility can be enhanced significantly. There is a ∼40% electron mobility enhancement for incorporated carbon content of 0.25% in strained-Si NMOSFETs compared to unstrained Si channels. The performance of channels with increased strain is not as high as theoretical predictions. This is due to the large Dit at the oxide/strained-Si:C interface and alloy scattering, which degrades carrier mobility enhancement.

Soft breakdown properties affected by photon energy during rapid thermal post-oxidation annealing (POA) of ultra-thin gate oxide are investigated. Generally, breakdown can be classified into normal hard breakdown (HBD) and soft breakdown (SBD). It was found that the occurrence of HBD and SBD depends on the process and stress field. Samples with front and back sides illuminated by a tungsten–halogen lamp during rapid thermal POA were examined. We find that front side illuminated oxides show easier SBD than back side ones. These results indicate that the photon energy may not only enhance the strength of Si–O bonds to suppress the lateral propagation of breakdown spots, but also to localize defects to form a conductive path of the leakage current. The understanding of the photon effect in rapid thermal POA is useful for controlling the electrical properties of ultra-thin gate oxides.

It is proposed that the metal-oxide-semiconductor (MOS) solar cells with sol-gel oxides deposited by spin coating are produced in this study. This sol-gel-derived SiO 2 layer is not very thin and the deviation in the thickness of the sol-gel layer is not slight. In general, the characteristics of MOS solar cells are significantly affected by the thickness of the SiO 2 layer. Particularly, the thermal grown oxide thickness required is less than 2nm for MOS solar cell applications. It is useful for large-scale and large-amount manufacturing that the influence of nonuniformity of oxide thickness on the characteristics of MOS solar cells with sol-gel oxides is reduced. It is observed that the short-circuit current density (J sc ) of 15.56 mA/cm2, the open-circuit voltage (V oc ) of 0.49V, the fill factor (FF) of 0.723 and the conversion efficiency (η%) of 5.44% are obtained by means of the current-voltage (I-V) measurements under AM 1.5 illumination at 25°C in the MOS solar cell with sol-gel oxides.

One-transistor (1T) memory cells with long data retention time is achieved with the modulation of drain current by channel traps. For simple demonstration, poly-Si TFTs are used, and grain boundary traps induced by excimer laser annealing are used as channel traps. The channel length in this work is 6 μm and the extrapolated data retention time can be as long as ~107 s at half of the current window. With the assumption that total number of traps is proportional to device volume and leakage current is proportional to the peripheral areas, retention time is scaled with gate length. For 30 nm devices, retention time is estimated to be ≥ 5×104 s. Compared with the conventional Zero-capacitor random access memory (Z-RAM), the channel trap memory provides better retention characteristics. For practical applications, the new channel trap cell has the same gate structure as logic devices, and can be potentially embedded in SoC platform. Due to the defect tolerance of cell channel and the low-temperature process, the 3D (multi-layer) memory structure by stacking the cells vertically can be potentially implemented more easily than flashtype devices [1]. In principle, the channel traps cells can also be implemented in bulk Si and the localized channel traps can be formed in the scaled devices using implantation techniques. This paper proposes a design of 1T memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.

Thin oxide property in a metal–oxide–semiconductor structure subjected to substrate injection from semiconductor into oxide is investigated by means of ramp-up and ramp-down current–voltage (I–V) measurements. Generally, gate injection causes catastrophic dielectric breakdown, and the damaged oxide suffers from permanent destruction which exhibits resistorlike behavior in the I–V curve. For substrate injection, however, there are three distinct modes existing in I–V characteristics. They are resistorlike, hysteresislike, and saturation, i.e., no breakdown. Their occurrence frequencies are dependent on the oxide thickness. For oxides thinner than 2.4 nm, in general, the gate current nearly saturates due to the limitation of minority carriers. For 3.9 nm oxide, the minority carrier generation rate increases due to trap generation near the Si surface. Thus the oxide sustains higher field and larger carrier injection causing destructive damage, i.e., resistorlike mode. For 3 nm oxide, sometimes a hysteresislike mode appears due to light damage in the oxide. The related characteristics of these three modes are studied and exhibit oxide thickness dependence. These phenomena are important to recent studies on devices with ultrathin gate oxides.