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Short-Circuit (SC) current sharing in parallel connected SiC MOSFETs and SiC Cascode JFETs have been investigated using experimental measurements and finite element models. Device parametric variation between parallel devices contributes to uneven current sharing and reduced module robustness against SC events. Experimental measurements show that threshold voltage variation is the most critical parameter in SiC MOSFETs, more so than device switching rate and initial junction temperature. The temperature coefficient of the ON-state and saturation resistance of SiC Cascode JFETs is higher than that of the SiC MOSFETs, hence, the short-circuit energy is lower because the SC current is limited more quickly in the SiC Cascode JFETs compared to SiC MOSFETs. Also, the input silicon MOSFET in the Cascode arrangement ensures better performance regarding VTH mismatch between parallel devices under SC. This is because the threshold voltage variation is less in silicon MOSFETs compared to SiC MOSFETs. Finite element models have been used to explore the differences between SiC MOSFETs and SiC Cascode JFETs under SC conditions and to explain why JFETs are better at suppressing SC currents than MOSFETs.

To control power flow and manage fault level in meshed MV networks, back-to-back voltage source converters (B2B-VSCs) are being used. However, their high cost and relatively low efficiency are of concerns. Partially rated series compensators, such as SSSCs or UPFCs, are desired but come with the challenge of protecting the device during grid faults. Their potential of use has been limited in comparison with the fully rated back-to-back converters. This paper proposes a new system topology including thyristor crowbars and a varistor to protect the SSSC in an MV network and improve the reliability and flexibility of the network operation. Using the proposed method, the time required for isolating the series compensator from the grid is reduced from at least 20 ms, corresponding to the interruption time of conventional circuit breakers, down to 3 μs in the worst case in addition to the grid fault detection delay. The performance is evaluated by simulation. A small-scale single-phase prototype operating at 230 V/16 A is tested in order to demonstrate the concept.

The main requirements of the wide-area monitoring system is to acquire the real-time measurement of state variables that can be provided by phasor measurement units (PMUs). The optimal PMU placement is the leading object of this paper, which is presented as an integer linear programming problem. The zero injection buses (ZIBs) and conventional measurements (CMs) enhance the system observability. In this paper, a novel integrated model is presented to consider the effects of the ZIBs and CMs for PMU placement. The proposed model considers limitations caused by ZIBs and CMs that have not been studied earlier. The single branch and single PMU outage, as two common contingencies, are also separately and simultaneously taken into account. The proposed method is applied to five different IEEE test systems (14, 30, 39, 57, and 118 bus) in order to demonstrate its effectiveness. The obtained results are compared with that of the other studies.