Search

This paper proposes an efficient architecture (InvArch) for computing matrix inversion using Gauss-Jordan Elimination method. The proposed architecture exploits parallelism through pipelined floating-point computational units and reduces the number of floating-point multiplication units required compared with the existing pipelined implementations. The reduction in multiplication units results in over 80% reduction in hardware for floating point computation units. The architecture performs in-place inversion and provides scalability across the rows and columns. Hardware efficiency is achieved by reaping benefit from regularity in computation and better utilization of pipelined computational resources. Multiple rows are normalized within an iteration of Gauss-Jordan algorithm that allows reduction in number of floating-point multiplication units in the elimination step. In addition to implementing the architecture, an analytical performance model is also developed for InvArch and some related works. InvArch achieves performance comparable to reference architectures in terms of clock cycles and throughput while using significantly less hardware resources.

Range Migration Algorithm (RMA) is one of the most practiced frequency domain based algorithms for Synthetic Aperture Radar (SAR) image reconstruction. While computationally more intensive than Polar Format Algorithm (PFA), it has superior image reconstruction for large squint angles. Due to the real-time nature of SAR imaging-related tasks, it is desired to have faster hardware implementations of reconstruction algorithms. In this paper we study FPGA-based implementation of the RMA algorithm using a novel pipelined Non-uniform FFT (NuFFT) module that optimizes its operation by exploiting the order in which samples are presented. We demonstrate that we can achieve processing speed of over 600 Msps (Mega Samples per Second) for the implemented RMA algorithm using the FPGA.

Many Hughes tactical and strategic programs need high performance image processing. For example, photo-interpretation applications can require up to four orders of magnitude speedup over conventional computer architectures. Therefore, parallel processing systems are needed to help close the processing gap. Vision applications can usually be decomposed into three levels of processing called high, intermediate, and low level vision. Each processing level typically requires different types of numeric/symbolic computation, processing task granularities, and communications bandwidths. No parallel processing system is commercially available that is optimized for the entire range of computations. To meet these processing challenges, the image understanding architecture (IUA) has been developed by Hughes in collaboration with the University of Massachusetts. The IUA is a heterogeneous, hierarchical, associative parallel processor that is organized in three levels corresponding to the vision problem. Its lowest level consists of a large content addressable array parallel processor. This array of 'per pixel' bit serial processors is used for fixed point, low level numeric, and symbolic computations. The middle level is an interface communications array processor (ICAP). ICAP is an array of digital signal processing chips from TI TMS320Cx line, used for high speed number crunching. The highest level is the symbolic processing array. It is an array of general purpose microprocessors in which the artificial intelligence content of the image understanding software resides. A set of benchmarks from the DARPA/ORD sponsored SCORPIUS program were developed using the IUA. The set of algorithms included low level image processing as well as high level matching algorithms. Benchmark performance on the second generation IUA hardware is over four orders of magnitude faster than equivalent algorithms implemented on a DEC VAX 8650. The first generation hardware is operational. Development of the second generation hardware and software for DARPA's Unmanned Ground Vehicle Program is under way in collaboration with the University of Massachusetts and Amerinex Artificial Intelligence.© (1992) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.