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The development of the Josephson circuits required to implement the feedback loop, the SFQ-to-1 mV output converter and the 100 [Phi.sub.0] quantum accurate DAC is reported.

A latest demonstration of superconductor oscillator/counter A/D Converter up through twelve Giga-Sample per second (12 GS/s) with 3 effective bits of signal-to-noise ratio at that sample rate is presented along with analysis of its performance. This A/D Converter incorporates a new technique for defining the aperture using inter-Josephson transmission line single-flux-quantum repulsion.

A recent demonstration of a Multiply-Accumulate (MAC) unit, which is the core of digital signal processor that implements programmable band-pass signal filtering, is presented. The design approach and risks associated with fringe field magnetic coupling between bias and signal lines are discussed.

An output amplifier that uses a new pulse multiplier circuit is reported. The pulse multiplier consists of several stages arranged in series in which a double-flux-quantum gate at each stage promotes the single flux quantum (SFQ) pulse to the next stage.

Research ivolving the application of first-in, first-out (FIFO) buffers to circular shift registers, serial memory and data re-clocking is described and discussed.

A method is described for calculating the bit error rate (BER) of multi-junction rapid single flux quantum (RSFQ) gates.

It is argued that series biasing is a viable solution to the problem of powering large rapid single flux quantum (RSFQ) chips and systems. Two approaches to resolving the obstacle of differential SFQ signal transfer are proposed.

Various practical questions having to do with chip-to-chip and on-chip communication are addressed.

Research describing improved 4kA/cm2 niobium circuit technology is presented. In particular a high density foundry process yielding integration of 3000 junctions per chip is evaluated.

Research describing yield optimization for digital superconductor electronics is presented. In particular Malt2 software implementation for Spice circuit simulation is described.

A study of oscillator/counter analog-to-digital converters is presented with emphasis on their theoretical aspects and performance. The advantages such as low power of a basic model and its variations are examined.

Research is presented concerning the development of a single flux quantum circuit that achieves ultra-high clock rates and ultra-low dissipation of power. The frequency-independence of the clock distribution is discussed.

The bit-error rate (BER) of an RS latched, clocked single-flux quantum circuit has been determined by using a digital error-correction circuit in measuring the BER between unity to 10 to the negative 13th power. The BER was measured as a function of control current with the application of both positive and negative control currents. The error rate has a minimum value of 10 to the negative 80th power at 5.5 K. A comparison of theoretical error-function estimates of BER indicate that the noise is purely thermal.

Research was conducted to experimentally examine on-chip parameter variations in Rapid Single Flux Quantum (RSFQ) circuits for the first time. A simple method to investigate the variations and their influence on the performance of RSFQ circuits was developed. Experimental results provide evidence that the construction of such RSFQ circuits covering the entire area of the integrated circuit is feasible using current fabrication technology.

Research was conducted to examine the manufacturability of superconductor-based computation modules including the integrated circuit foundry process, packaging and data link out of the cryopackage. The study focused on the critical technical challenges that exist in each of the areas. A technology roadmap aimed at achieving the Hybrid Technology Multi-threaded requirements is presented.

A decimation filter four-bit rapid single flux quantum (RSFQ) multiplier-accumulator was designed and tested. Six types of 38 synchronous RSFQ cells arranged into a rectangular systolic array fed by on serial input and one parallel input make up the device. A counter-flow clock distribution scheme with a 11 GHz simulated maximum clock frequency was used for timing. The circuit features a 1100 Josephson junctions, an area less than 2.5 mm2 and power consumption below 0.2 mW.

A high-speed test scheme is proposed for maximum clock frequency measurement in a four-bit rapid single flux quantum decimation digital filter. The approach only requires standard low-cost measurement devices and a low-speed interface. Results demonstrate the testing scheme's superiority over other high-speed tests in terms of added circuitry, in control, measurement equipment parameters and high-speed input/output requirements.

The results of an active SFQ bit-error rate experiment were compared to theoretic prediction. The Fokker-Planck equation was employed to develop a theory of thermally-induced errors. The experiment showed that the equivalent noise temperature was 11.0 K. Results also reveal that the error rate vs the bias current was dependent on error function and extrapolate at optimal bias to a very small error rate.

The inscribed hyperspheres algorithm was used as a tool in the multiparameter optimization of rapid single flux quantum (RSFQ) circuits. The method of inscribed spheres is based on the interaction of a set of parameter values inside the operating region, which are called the starting point, and the points in the boundary of the operating region. It is effective for as many as nine parameters. An illustration of the starting point and first three iterations of the method is included.

A survey of CAD tools targeting superconducting digital electronics was conducted. Circuit optimizers, circuit simulators, inductance estimators, layout tools and logic simulators comprised the five categories of tools that were studied. Other tools that were discussed included tools for timing analysis and integrated design environments that allowed the effective data interchange among different tools. Survey results demonstrate that future tools for timing optimization, automated layout synthesis and automated logic synthesis are required for superconducting circuit design at the very large scale of integration level of integration.

A new design methodology created specifically for rapid single flux quantum (RSFQ) circuits is proposed. The basis of the methodology is a semiconductor semicustom design approach. For the design of the basic RSFQ cells, an established design methodology for small-scale RSFQ digital circuits based on circuit simulation and device parameter optimization was used. The method was then successfully used at the University of Rochester for the design of two large-scale digital circuits.