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Carrier depletion ring modulators offer low power, low footprint, and high modulation speed in the perspective of future silicon photonic interconnects. However, the optical power penalty, which stands for the impact of this device on power budget, is sensitive to the ring power coupling coefficient. In this paper, we derive a relationship between the optical power and this device parameter using a simple analytical model. This model is first described and then compared to ring modulators fabricated in a 300-mm silicon photonic platform through systematic characterization of resonance depth, quality factor, and power penalty. A significant power penalty sensitivity to coupling coefficient variability as high as ∼0.6 dB/% is evaluated from this model and confirmed by measurements. The limitations of this model are also discussed.

International audience; This paper presents a Mach-Zehnder-based transmitter in 0.18 µm CMOS. An asymmetric driver is proposed to achieve a large output swing on the optical modulator. The logical effort method was applied on each driver block in order to optimize the propagation delay. The driver characteristics are analyzed based on slew-rate limitation. The speed-power-area trade-off is highlighted and enables to adjust the driver design according to specified constraints. Driver performance obtained with early-design-stage equations is compared to post-layout simulations. Good agreement is demonstrated which validates the proposed sizing methodology.

The presented method allows to evaluate the impact of power coupling on the performances of a carrier depletion ring resonator transmitter. From a measurement-based modulator model, coupling coefficient is varied and optimized maximizing modulation amplitude and reducing the impact of its process variability.

After 15 years of research, silicon photonics has now reached a sufficient level of maturity at the device level to be implemented into low-cost optical communication products. In this chapter we review the challenges of the industrialization of silicon photonics in 300 mm facilities, using mainstream CMOS methodologies. We first review the challenges of a sustainable electronic and photonic integration allowing the production of low-cost chips for the current 100G generation but also for the future 400G and beyond. Next, the industrial testing strategy and the design of test circuits allowing an efficient process monitoring are discussed. The industrial process integration scheme of optical components on 300 mm wafers is then described, followed by the device model strategy, which is a key element in order to make the link between the photonic design kit and the process. Finally, further R&D efforts in 300 mm allowing new functionality for the longer term Si photonics development are discussed. As examples, the integration of several Si etching levels, the demonstration of smart SOI substrates feasibility for improved coupling efficiency, and integration of ring modulator are detailed.

We study the process variability impact of silicon ring modulators on resonance wavelength, which is a key parameter to design WDM communication systems based on those devices.

This paper describes how to reduce spurious resonances which can take place in a resonator using guided waves above a Bragg mirror. These parasitics arise from overtone resonances as well as from higher order modes also excited by electrodes having inappropriate dimensions. In this paper, the influence of period and metalization ratio on the harmonic admittance of a resonator is studied.