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This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moire are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.

The high-temperature thermal stability of a metal-insulator-metal (MIM) capacitor has been disclosed and improved by embedding a WN barrier layer between bottom electrodes and high-k dielectrics. The interfacial reaction between high-k dielectrics and bottom electrode during high temperature annealing was suppressed. Therefore, both equivalent oxide thickness (EOT) and leakage current were well controlled to meet the criterion of deep trench DRAM technology beyond 50nm.

The objective of this paper is to measure and simulate the warpage of 3D TSV (through-silicon via) die-stacked DRAM (dynamic random access memory) packages subject to thermal loading (from the room temperature to 260°C, solder reflow temperature) during manufacturing processes. The related die stresses and keep-out zone (KOZ) for the dies in the packages at the room temperature are further calculated with this validated simulation model. In the experiments, a full-field shadow moire is used to measure the out-of-plane deformation (warpage) of packages under thermal heating conditions. A finite-element method (FEM) is applied for analyzing the thermally-induced deformation, stresses and KOZs in the packages to gain insight into their mechanics. The full-field warpages of the packages from the shadow moire have been documented under temperature loading and compared well with FEM results. The stresses and KOZs at the proximity of a single TSV for each die in the package at the room temperature have been calculated with validated FEM model. It is found that the sizes of KOZs in four-die stacked DRAM package at the room temperature are dominated by the horizontal pMOS device and are almost double as large as the size in wafer-level die. And the sizes of KOZs are pretty much similar for each die in this four-die stacked DRAM package, even through the stresses at each die are apparently different.

This study is to numerically and experimentally investigate the effect of via-middle Cu through silicon via (TSV) on the mobility change (or related saturated current change, or drive current change) of transistors in the DRAM chip for 3D integration and further determine the keep-out zone (KOZ) in terms of key parameters such as SiO 2 layer effect, zero-stress temperature, single and array vias, through and blind vias, as well as diameter and pitch of vias. From the results of this study, the zero-stress temperature has been successfully determined from experimental data. The KOZs based on the more than 10% change in carrier mobility (or 5% saturated current changes) have been identified by finite element numerical calculations associated with related piezoresistive coefficients. Numerical results of saturated current changes have been validated by good comparisons with experimental data. Based on the detailed analyses using this validated model, the key parameters affecting the KOZs will be presented and discussed in detail.

As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes stresses on silicon near the TSV, the impact of TSV proximity on CMOS must be evaluated at various operation temperatures. In this paper, Cu-filled TSVs were fabricated in “via middle” process. The TSVs-induced mechanical stresses causing carrier mobility change that result in drive current (I on ) variation. In order to obtain robust design rules (i.e. keep-out zone) and spice model for TSV applications, electrical characteristics of CMOS devices were investigated in terms of distance between TSV and CMOS device in this work.