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As key applications become more data-intensive and the computational throughput of processors increases, the amount of data to be transferred in modern memory subsystems grows. Increasing physical bandwidth to keep up with the demand growth is challenging, however, due to strict area and energy limitations. This paper presents a novel and lightweight compression algorithm, Bit-Plane Compression (BPC) , to increase the effective memory bandwidth. BPC aims at homogeneously-typed memory blocks, which are prevalent in many-core architectures, and applies a smart data transformation to both improve the inherent data compressibility and to reduce the complexity of compression hardware. We demonstrate that BPC provides superior compression ratios of 4.1:1 for integer benchmarks and reduces memory bandwidth requirements significantly.

Memory system performance is measured by access latency and bandwidth, and DRAM access parallelism critically impacts for both. To improve DRAM parallelism, previous research focused on increasing the number of effective banks by sub-dividing one physical bank. We find that without avoiding conflicts on the shared resources among (sub)banks, the benefits are limited. We propose mechanisms for efficient DRAM resource utilization and resource-conflict avoidance (ERUCA). ERUCA reduces conflicts on shared (sub)bank resources utilizing row address locality between sub-banks and improving the DRAM chip-level data bus. Area overhead for ERUCA is kept near zero with a unique implementation that exploits under-utilized resources available in commercial DRAM chips. Overall ERUCA provides 15% speedup while incurring

DRAM row and column sparing cannot efficiently tolerate the increasing inherent fault rate caused by continued process scaling. In-DRAM ECC (IECC), an appealing alternative to sparing, can resolve inherent faults without significant changes to DRAM, but it is inefficient for highly-reliable systems where rank-level ECC (RECC) is already used against operational faults. In addition, DRAM design in the near future (possibly as early as DDR5) may transfer data in longer bursts, which complicates high-reliability RECC due to fewer devices being used per rank and increased fault granularity. We propose dual use of on-chip redundancy (DUO), a mech- anism that bypasses the IECC module and transfers on-chip redundancy to be used directly for RECC. Due to its increased redundancy budget, DUO enables a strong and novel RECC for highly-reliable systems, called DUO SDDC. The long codewords of DUO SDDC provide fundamentally higher detection and correction capabilities, and several novel secondary-correction techniques integrate together to further expand its correction capability. According to our evaluation results, DUO shows performance degradation on par with or better than IECC (average 2–3%), while consuming less DRAM energy than IECC (average 4–14% overheads). DUO provides higher reliability than either IECC or the state-of-the-art ECC technique. We show the robust reliability of DUO SDDC by comparing it to other ECC schemes using two different inherent fault-error models.

Transmission control protocols have to overcome common problems in wireless networks. TCP employing both packet loss discrimination mechanism and available bandwidth estimation algorithm, known as the good existing solution, shows significant performance enhancement in wireless networks. For instance, TCP New Jersey which exhibits high throughput in wireless networks intends to improve TCP performance by using available bandwidth estimation and congestion warning. Even though it achieves 17% and 85% improvements in terms of goodput over TCP Westwood and TCP Reno, respectively, we further improve it by exploring maximized available bandwidth estimation, handling bit-error-rate error recovery, and effective adjustment of sending rate for retransmission timeout. Hence, we propose TCP NJ+, showing that for up to 5% packet loss rate, it outperforms other TCP variants by 19% to 104% in terms of goodput when the network is in bi-directional background traffic.

Adaptive-granularity memory architectures have been considered mainly because of main memory bottleneck and power efficiency. Meanwhile, highly reliable protection schemes are getting popular especially in large computing systems. Unfortunately, conventional ECC mechanisms including Chipkill require a large number of symbols to guarantee strong protection with acceptable overhead. We propose a novel memory protection scheme called CLEAN (Chipkill-LEvel reliable and Access granularity Negotiable), which enables us to balance the contradicting demands of fine-grained (FG) access and strong & efficient ECC. To close a potentially significant detection coverage gap due to CLEAN's detection mechanism coupled with permanent faults, we design a simple mechanism access granularity enforcement. By enforcing coarse-grained (CG) access, we can get only the advantage of higher protection comparable to Chipkill instead of achieving the adaptive access granularity together. CLEAN showed Chipkill level reliability as well as improvement in performance, system and memory power efficiency by up to 11.8%, 10.8% and 64.9% with mixes of SPEC2006 benchmarks.

Because main memory is vulnerable to errors and failures, large-scale systems and critical servers utilize error checking and correcting (ECC) mechanisms to meet their reliability requirements. We propose a novel mechanism, Frugal ECC (FECC), that combines ECC with fine-grained compression to provide versatile protection that can be both stronger and lower overhead than current schemes, without sacrificing performance. FECC compresses main memory at cache-block granularity, using any left over space to store ECC information. Compressed data and its ECC information are then frequently read with a single access even without redundant memory chips; insufficiently compressed blocks require additional storage and accesses. As examples, we present chipkill-correct ECCs on a non-ECC DIMM with x4 chips and the first true chipkill-correct ECC for x8 devices using an ECC DIMM. FECC relies on a new Coverage-oriented-Compression that we developed specifically for the modest compression needs of ECC and for floating-point data.

Growing computer system sizes and levels of integration have made memory reliability a primary concern, necessitating strong memory error protection. As such, large-scale systems typically employ error checking and correcting codes to trade redundant storage and bandwidth for increased reliability. While stronger memory protection will be needed to meet reliability targets in the future, it is undesirable to further increase the amount of storage and bandwidth spent on redundancy. We propose a novel family of single-tier ECC mechanisms called Bamboo ECC to simultaneously address the conflicting requirements of increasing reliability while maintaining or decreasing error protection overheads. Relative to the state-of-the-art single-tier error protection, Bamboo ECC codes have superior correction capabilities, all but eliminate the risk of silent data corruption, and can also increase redundancy at a fine granularity, enabling more adaptive graceful downgrade schemes. These strength, safety, and flexibility advantages translate to a significantly more reliable memory system. To demonstrate this, we evaluate a family of Bamboo ECC organizations in the context of conventional 72b and 144b DRAM channels and show the significant error coverage and memory lifespan improvements of Bamboo ECC relative to existing SEC-DED, chipkill-correct and double-chipkill-correct schemes.

The sensors in sensor networks have limited energy and thus energy preserving techniques are important. The low-energy adaptive clustering hierarchy (LEACH) technique improves energy efficiency of the sensor network by selecting a cluster head, and having it aggregate data from other nodes in its cluster and transmit it to the base station. In this paper, we propose three techniques, which we will call collectively Energy Efficient LEACH (EEL), that improve on LEACH to significantly reduce energy consumption and increase the lifetime of the sensor network. Simulation results using the NS-2 network simulator show that EEL improves LEACH by 37% with respect to network lifetime.

Transmission mechanisms that include an available bandwidth estimation algorithm and a packet loss differentiation scheme, in general, exhibit higher TCP performance in wireless networks. TCP New Jersey, known as the best existing scheme in terms of goodput, improves wireless TCP performance using the available bandwidth estimation at the sender and the congestion warning at intermediate routers. Although TCP New Jersey achieves 17% and 85% improvements in goodput over TCP Westwood and TCP Reno, respectively, we further improve TCP New Jersey by exploring improved available bandwidth estimation, retransmission timeout, and recovery mechanisms. Hence, we propose TCP New Jersey PLUS (shortly TCP NJ+), showing that under 5% packet loss rate, a characteristic of high bit-error-rate wireless network, it out-performs other TCP variants by 19% to 104% in terms of goodput even when the network is in bi-directional congestion.

TCP application in wireless HCI environments communicates to each other frequently through wireless networks. Therefore, it is important that significant TCP performance is guaranteed in wireless network. TCP New Jersey, known as the best existing scheme in terms of goodput in wireless networks, improves wireless TCP performance using the available bandwidth estimation at the sender and the congestion warning at intermediate routers. Although TCP New Jersey achieves 17% and 85% improvements in goodput over TCP Westwood and TCP Reno, respectively, we further improve TCP New Jersey by exploring enhanced available bandwidth estimation and suitable error recovery mechanism. Hence, we propose TCP NJ+. It outperforms other TCP variants by 19% to 104% in terms of goodput even when the network is in bi-directional congestion. Hence TCP NJ+ can provide the best services to user in wireless HCI environments.