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In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 μm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.

A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and picture-quality improvement, such as noise reduction and image enhancement.

In multimedia applications, various video encoding/decoding standards such as MPEG2, MPEG1 and emerging algorithms call for a DSP solution of the extremely computation-intensive tasks. Several DSPs have been developed based on intensive pipeline processing at the macro-block level. In these DSPs, macroblock-based pipeline memory slices are needed for each pipeline stage. Programmability is limited by the hard-wired macros to be incorporated such as DCT and Quantizer. A microprocessor or a media-processor with multimedia-enhanced instructions has not yet been applied to MPEG2 encoding. This DSP for real-time codec applications has the following features: (a) extensive use of data parallelism inside the macro-block data structure, (b) flexible data path for coding algorithms to enhance gate utilization and to reduce the use of macro-block pipeline memory, (c) data path design suitable for (but not limited to) fast DCT/IDCT algorithms.

We developed a soft macro cell generator which generates discrete cosine transform (DCT) macro cells for various video compression requirements. Because of the proposed fast algorithm, hardware implementation, and customized flip flop cells, a generated macro cell is as small as any other full custom DCT LSI and macro cell, although the generator's output is a soft macro cell. Furthermore an equivalent C language model and an accuracy report necessary for parameter optimization of complex DCT arithmetic are also generated. An MPEG-quality DCT macro cell has been generated and fabricated on 0.7 /spl mu/m 3-metal CMOS for performance evaluation, such as cell speed, size, and design time.

Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.