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Heavy-ion irradiation and fault injection experiments were conducted to evaluate the upset sensitivity of the Xilinx Virtex-II field programmable gate arrays (FPGAs) input/output block (IOB). Full triple module redundancy (TMR) of the IOBs, in combination with regular configuration scrubbing, proved to be a quite effective upset mitigation method. Index Terms--Fault injection, radiation effects, reconfigurable field programmable gate arrays (FPGAs), single-event effects.

Proton-induced single event effects of a set of microcircuits are compared with effects due to heavy ions. Even though some microcircuits show a relatively high sensitivity to heavy ions, they do not have a corresponding sensitivity to protons. Index Terms--Effects, heavy ion induced upsets, radiation effects, radiation sensitivity to protons, SEU prediction models, single event.

Field-programmable gate arrays (FPGAs) and operational amplifiers are commonly used microelectronics in spaceflight instrumentation. In ground-based testing, these devices have been shown to experience single-event upset (SEU), the digital variety for the FPGA and the analog or transient type for the op-amps. Two experiment boards on the Microelectronics and Photonics Test Bed (MPTB) test these same parts in space. The data collected to date are presented here. The most interesting results are not from the primary focus of the SEU but from the total ionizing dose (TID) current monitoring of the FPGAs. Index Terms--Antifuse rupture, comparator, COTS, electron dose enhancement, field-programmable gate array (FPGA), flight experiment, ground test, heavy ion radiation, MPTB, operational amplifier, proton irradiation, radiation effects, single-event effect (SEE), single-event transient (SET), single-event upset (SEU), spot shielding, test bed, total ionizing dose (TID).

SEU sensitivity of microcircuits to relativistic heavy ions is compared to that measured with low energy ions of comparable LET values. Multiple junction charge collection in a complex circuit seems to mask the effect of varying charge generations due to different ion track structures. Heavy ions at sub-relativistic speeds may generate nuclear fragments, sometimes resulting in SEUs.

The single event upset (SEU) sensitivity of certain types of linear microcircuits is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SEU control have been suggested.

Manufacturers of field programmable gate arrays (FPGAs) take different technological and architectural approaches that directly affect radiation performance. Similar technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices' total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Quartz crystal resonators were systematically irradiated with 65 MeV protons to characterize low dose rate radiation-induced degradation. Results indicate: (1) test samples that exhibit large frequency shifts during testing tend to show large frequency shifts prior to irradiation, or during off-irradiation periods; (2) for radiation-sensitive samples, short-term effects seem to decrease after each irradiation on/off cycle (moreover, those devices in which radiation effects do not decrease after a few cycles are not very sensitive); (3) the fabrication process may be an important determinant of susceptibility to low dose radiation-induced degradation; and (4) total-dose effects may be sublinear.

Digital signal processors (DSPs) sensitive to SEE may be utilized in some space-borne systems, in which the effects of cosmic-rays and trapped protons are limited. Thorough ground testing for SEE is essential in designing an SEE tolerant system, with a minimized risk factor.

SEE testing was performed on pulse width modulation (PWM) controllers which are commonly used in switching mode power supply systems. The devices are designed using both Set-Reset (SR) flip-flops and Toggle (T) flip-flops which are vulnerable to single event upset (SEU) in a radiation environment. Depending on the implementation of the different devices the effect can be significant in spaceflight hardware.

A systems-oriented single event effects (SEE) test approach is outlined here for two different phase-locked loop (PLL) application specific integrated circuits (ASICs) used for spaceborne local oscillator (LO) generation. The system considerations in designing the upset detection technique is described. This is the only known technique for getting information critical to the system about single event upset (SEU) sensitivity at speed for PLLs. Test results are presented for PLL devices operating at clock speeds of 1.0 and 1.5 GHz. Significant frequency effects were not observed in these devices since the clock speed varied only 50%.

Laser tests performed on a prototype chip to validate new SEU-hardened storage cell designs revealed unexpected latch-up and single-event upset phenomena. The investigations that identified their location show the existence of a topology-dependent dual node upset mechanism. Design solutions are suggested to avoid its occurrence.

High and low resistive load versions of Micron Technology's MT5C1008C (128K x 8) and MT5C2561C (256K x 1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a '1' [right arrow] '0' to '0' [right arrow] '1' bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.

Ground-based single event effect (SEE) testing of microcircuits permits characterization of device susceptibility to various radiation induced disturbances, including: 1) single event upset (SEU) and single event latchup (SEL) in digital microcircuits; 2) single event gate rupture (SEGR), and single event burnout (SEB) in power transistors; and 3) bit errors in photonic devices. These characterizations can then be used to generate predictions of device performance in the space radiation environment. This paper provides a general overview of ground-based SEE testing and examines in critical depth several underlying conceptual constructs relevant to the conduct of such tests and to the proper interpretation of results. These more traditional issues are contrasted with emerging concerns related to the testing of modern, advanced microcircuits.

Proton and ion Single Event Phenomena (SEP) tests were performed on 32-b processors including R3000A's from all commercial manufacturers along with the Performance PR3400 family, Integrated Device Technology Inc. 79R3081, LSI Logic Corporation LR33000HC, and Intel i80960MX parts. The microprocessors had acceptable upset rates for operation in a low earth orbit or a lunar mission such as CLEMENTINE with a wide range in proton total dose failure. Even though R3000A devices are 60% smaller in physical area than R3000 devices, there was a 340% increase in device Single Event Upset (SEU) cross section. Software tests of varying complexity demonstrate that registers and other functional blocks using register architecture dominate the cross section. The current approach of giving a single upset cross section can lead to erroneous upset rates depending on the application software.

Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened solutions, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the efficiency of the approach.

Single Event Upset (SEU) characteristics of a digital emitter coupled logic (ECL) device clocking at 0.5, 1, and 3.2 GHz and at temperatures of 5, 75, and 105 [degrees] C are presented. The test technique is explained. Observations of two types of upsets, phase upsets at low Linear Energy Transfer (LETs) and amplitude upsets at high LETs are also presented. The cause of phase upsets is discussed. The effect of each type of upset on the system is discussed. The upset cross section and LET threshold seem to be insensitive to temperatures below 75 [degrees] C and to the clock frequencies tested.

Field Programmable Gate Arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was develolped for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.

Observation of an ion-induced sustained high current condition ('high current anomaly') in a bipolar device, that is similar but not identical to latchup, is reported. Both high current anomaly and single event upset test results are presented for the AD9048 test device. Photon emission microscopy was used to locate the site of the high current anomaly. A model of the triggering mechanism based on the results so obtained is described.

Space-borne electronics systems incorporating high-density static random access memory (SRAM) are vulnerable to single-word multiple-bit upsets (SMUs). We review here recent observations of SMU, present the results of a systematic investigation of the physical cell arrangements employed in several currently available SRAM device types, and discuss implications for the occurrence and mitigation of SMU.

Application specific integrated circuits (ASICs) offer a number of advantages over traditional multi-component microcircuits including reductions in both size and power dissipation, and are therefore prime candidates to replace such microcircuits in space-borne electronics systems. The results of recent tests of the susceptibilities of various ASIC devices to cosmic ray and trapped proton induced single event upset (SEU) and latchup are reported here and are compared to the susceptibilities of the devices that they would replace. This comparison leads to a discussion of the impact of ASIC devices on the SEU susceptibility of space-borne computers.

Event rates encountered by satellite-borne sensors typically exceed the available telemetry bandwidth, necessitating on-board data analysis. One method of reducing output telemetry requirements, employed by data processing units (DPUs) on several recent and forthcoming satellites (VIKING, CRRES, CAMMICE) is to partition the underlying event parameter spaces into disjoint classes, and to downlink statistics based on these classes rather than individual events. The DPUs utilize a hardware implemented binary search algorithm to classify each valid event into one of several mass and mass per charge-state (M/Q) groups, using look-up tables written under software control. Mass and M/Q group boundaries are defined via polynomial curves in the underlying parameter spaces. The boundary curves were obtained using a combination of global and local least-squares approximation algorithms applied to pre-flight sensor calibration data.

Observations of single event burnout (SEB) in embedded field effect transistors are reported. Both SEB and other single event effects are presented for several pulse width modulation and high frequency devices. The microscope has been employed to locate and to investigate the damaged areas. A model of the damage mechanism based on the results so obtained is described.

State of the art programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.