Search

This article intends to reflect on the creation of the first undergraduate courses in Social Work at the gaucho federal universities in the interior of Rio Grande do Sul, more specifically at the Federal University of Pampa (Unipampa/Sao Borja Campus), the first public, federal and free course in the interior of the state of Rio Grande do Sul in the area of Social Work, and at the Federal University of Santa Maria (UFSM), third funded course. The article also discusses the possibilities of the expansion of higher education courses in Social Work in the state of Rio Grande do Sul, concerning local-regional development, bringing, furthermore, its contradictions and challenges to the way such courses were being implemented.

Digital Inclusion through of Playful Workshops to Encourage Computational Thinking Abstract: This initiative arises from the need to improve the educational rates observed in recent years, especially those reported by the Instituto Brasileiro de Geografia e Estatística (IBGE) and by the Índice de Desenvolvimento da Educação Básica (IDEB). This paper presents an experience developed with the school community, with the offer of playful workshops to stimulate computational thinking. The methodology of the workshops consists basically of dynamic alternatives to the traditional classroom teaching, promoting playful moments for the participants through the use of games and digital resources, in order to promote the digital inclusion for students of the final grades of elementary school in public schools of the North Coast region of the Rio Grande do Sul State. The activities are developed with information technology resources, in two stages: with the use of digital games through free platforms, and with the use of unplugged computing, thus enabling the schools to attend regardless of the available technological resources, as a computer lab, for example. In the meetings, playful games are used, stimulating participants' learning based on the basic principles of programming, which are essential for living in society today. In 2019, 200 participants were attended. The results shown that the experience provided improvements of up to 48% in the participants 'comprehension of statements, as well as increasing the students' interest in technology, promoting integral and citizen education, providing opportunities for creative and meaningful learning. Keywords: Playful Workshops. Digital Inclusion. Computational Thinking. Resumo: Esta iniciativa surge diante da necessidade de melhoria nos índices educacionais observados nos últimos anos, em especial aqueles informados pelo Instituto Brasileiro de Geografia e Estatística (IBGE) e pelo Índice de Desenvolvimento da Educação Básica (IDEB). Este trabalho apresenta uma experiência desenvolvida junto à comunidade escolar, com a oferta de oficinas lúdicas para o estímulo do pensamento computacional. A metodologia dos encontros consiste basicamente em dinâmicas alternativas ao ensino tradicional da sala de aula, promovendo momentos lúdicos para os participantes através do uso jogos e recursos digitais, a fim de promover a inclusão digital para alunos das séries finais do Ensino Fundamental de escolas públicas da região do Litoral do Rio Grande do Sul. As atividades são desenvolvidas com recursos da tecnologia da informação, em duas etapas: com o uso de jogos digitais, através de plataformas gratuitas, e com o uso da computação desplugada, oportunizando, assim, o atendimento das escolas independentemente dos recursos tecnológicos disponíveis, como um laboratório de informática, por exemplo. Nos encontros, jogos lúdicos são utilizados, estimulando o aprendizado dos participantes com base nos princípios básicos da programação, que são essenciais para a convivência em sociedade nos dias de hoje. No ano de 2019, já foram atendidos 200 participantes. Os resultados obtidos mostram que a experiência proporcionou melhorias de até 48% na compreensão de enunciados pelos participantes, além de despertar o interesse dos alunos pela tecnologia, promovendo uma educação integral e cidadã, oportunizando um aprendizado de forma criativa e significativa. Palavras-chave: Encontros Lúdicos. Inclusão Digital. Pensamento Computacional.

The aim of this study was to compare the effects of single vs. multiple sets water-based resistance training on maximal dynamic strength in young men. Twenty-one physically active young men were randomly allocated into 2 groups: a single set group (SS, n=10) and a multiple sets group (MS, n=11). The single set program consisted of only 1 set of 30 s, whereas the multiple sets comprised 3 sets of 30 s (rest interval between sets equaled 1 min 30 s). All the water-based resistance exercises were performed at maximal effort and both groups trained twice a week for 10 weeks. Upper (bilateral elbow flexors and bilateral elbow extensors, peck deck and inverse peck deck) as well as lower-body (bilateral knee flexors and unilateral knee extensors) one-repetition maximal tests (1RM) were used to assess changes in muscle strength. The training-related effects were assessed using repeated measures two-way ANOVA (α=5%). Both SS and MS groups increased the upper and lower-body 1RM, with no differences between groups. Therefore, these data show that the maximal dynamic strength significantly increases in young men after 10 weeks of training in an aquatic environment, although the improvement in the strength levels is independent of the number of sets performed.

The main reason to invest in 3D circuits adoption is the possibility of decrease the wire length, replacing horizontal wires by shorter vertical through-silicon-vias (called of TSVs). As a consequence, a better performance is expected and other optimizations also can be obtained in comparison with planar technology. In relation to 3D circuits, the networks-on-chip (NoCs) receiving special attention because they are very used to provide efficient communication with wide parallelism. However, the development of 3D circuits is not trivial, being very common appear imperfections and manufacture problems, mainly in sensitive regions as the TSVs. Thus, the main contribution of this work is to allow the usability of the NoC in 3D circuits even in the presence of multiple defective TSVs, with minimal impact on the latency results. In this way, the behavior of the routing algorithm called Elevator-First, to tolerate defective TSVs, will be analyzed. In order to provide an appropriated alternative path to forward the traffic flow in the presence of multiple faulty TSVs, the use of traffic flow monitors has been proposed. The results obtained for the considered scenarios of simulation prove that the strategy can be very efficient, shown that is possible to improve more than 50% of latency in relation to the original algorithm evaluated without traffic flow analysis.

The third dimension is becoming an attractive solution to integrate components in a single integrated circuit. Therefore, 3D Networks-on-Chip (NoCs) are usually adopted to provide fast connections between the layers by using Through-Silicon-Vias (TSVs). However, many challenges during the 3D manufacturing phase are making the circuits more vulnerable and prone to failure. This work investigates the impact on latency in 3D NoCs under multiple faulty TSVs and it proposes a technique to ensure the connectivity of the NoC under multiple faults scenario. A fault model was proposed with four different configurations to distribute multiple faulty TSVs in the 3D NoC. Three different fault tolerant scenarios were explored: the first is the original routing algorithm called Elevated-First used to avoid faulty vertical connections. The second and third scenarios are our new designs based on the use of dynamic monitors to observe the flow through the paths, in order to be able to select best alternative paths under multiple faults. Fault injection results show that it is possible to reduce the latency impact from 1x to 10x in the best case configuration by use the proposed solutions.

International audience; Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.

The design of 3D circuits have been motivated by the need of decreasing the wire length in System-on-Chip (SoC) composed of more and more high number of processing elements. In general, advantages such as aiding the test methodology and increasing fault tolerance can be observed. However, the development of 3D circuits is not trivial, and there are still challenges in the manufacture process. The objective of this work is to address a low cost solution to improve the yield in TSVs, combining fault tolerance in horizontal interconnections, in order to minimize the fault susceptibility in 3D-NoCs. Comparisons among different serialization levels have been developed to show the advantages.

In a NoC, the amount of buffers allocated to each communication channel has a significant impact on performance and power consumption. Moreover, since there will be changes in the application communication pattern, or even because a new application is loaded in a SoC, a design based on the worst case scenario will probably either oversize buffers, with obvious power implications, or the performance will be compromised, since not enough buffers will be available. A runtime mechanism is required to automatically adapt the buffer size as a function of the communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router. The runtime mechanism is able to monitor the traffic behavior and to control, for each channel, the required buffer size of the adaptive router. Besides, as the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the router channels are crucial to ensure the communication performance. This way, a technique to isolate faulty buffers is also presented. Experimental results using the proposed architecture have shown that, in the absence of faults, the latency has been decreased by 80%, and throughput has been increased by 45%, in the worst case. In the presence of faults, the proposed architecture was able to sustain the same performance of the equivalent homogeneous router, but with up to 25% power savings.

International audience; The use of fault-tolerant mechanism is essential to ensure the correct functionality of integrated circuits after manufacturing due to the massive number of faults that may occur during the process. In this work, we propose a set of fault-tolerant techniques to cope with faulty wires in Network-on-Chip (NoC). The most appropriate technique is chosen by taking into account the number of faulty wires and their location in the NoC. The goal is to combine different techniques to reduce overheads in area, delay and power. The use of testing and diagnosis can minimize costs associated with embedded fault-tolerant mechanisms once the architecture adapts itself to work in different faulty scenarios. The proposed fault-tolerant strategy uses a lightweight adaptive routing combined with data splitting, which is able to send the data in one clock cycle. The power penalty has a low correlation with the number of faulty interconnections. Results for MPEG4 and VOPD applications running on the NoC with different faulty case-study scenarios show that the proposed techniques can tolerate many faulty interconnections with a low area, performance and power overheads.

The Network-on-Chip (NoC) topology for Multi Processor System-on-Chip (MPSoC) is a key factor for power consumption and communication time. In this work, we propose a NoC architecture that can adapt itself during run-time according to traffic patterns, based on an external control that changes the topology chosen. As a function of the application, the router connections can change from mesh to irregular topology (and vice-versa) to improve communication time and to save energy. This approach can improve the performance of an application under different traffic conditions. For the Mpeg4 case-study application is possible to decrease the communication time in 16%, saving around 62% in energy by choosing the right topology at each communication phase of the application. The extra area required for the adaptability is compensated by zero redesign costs, making it possible to reuse the NoC for any behavior without significant penalties.

A novel approach to handle multiple defects in the NoC links is presented. The fault-tolerant method can guarantee the functionally of the NoC with multiple defects in any link and with multiple faulty links. The proposed technique uses information from test to know where and when fault-tolerant features must be turned on. Comparisons with popular solutions based on EDAC show that the proposed method can provide a faster communication, while coping with multiple defects in the link without the need of extra wires. In addition, the adaptive approach saves energy because it is used only when required.

NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. Moreover, routers with virtual channels have larger buffer sizes and more complex control, increasing the total costs. The situation worsens whenever the application changes its communication pattern, i.e., when a portable phone downloads a new service. In this paper we propose the use of a two-level adaptive buffer for a virtual channel router, where the buffers units and the virtual channels are dynamically allocated to increase router efficiency in a NoC, even under rather different communication loads. With the proposed architecture the buffer and virtual channels in the input channels of the routers can be adapted at run time. The adaptive virtual channel router decreases the latency in the worst case by 10%, and a reduction of 80% in the best case is achieved when compared to previous works.

A strategy to handle multiple defects in the No Clinks with almost no impact on the communication delay is presented. The fault-tolerant method can guarantee the functionally of the NoC with multiple defects in any link, and with multiple faulty links. The proposed technique uses information from test phase to map the application and to configure fault-tolerant features along the NoC links. Results from an application remapped in the NoC show that the communication delay is almost unaffected, with minimal impact and overhead when compared to a fault-free system. We also show that our proposal has a variable impact in performance while traditional fault-tolerant solution like Hamming Code has a constant impact. Besides our proposal can save among 15% to100% the energy when compared Hamming Code.

The amount of buffers allocated to each NoC channel has a significant performance and power consumption impact. Moreover, when a NoC-based application could present changes in the communication pattern, or when a new application could be loaded in a SoC, a NoC design based on the worst case scenario probably will present oversize buffers. Besides, it will cause obvious power implications, or the performance will be compromised, since not enough buffers will be used. A runtime mechanism is required to automatically adapt the buffer size as a function of the actual communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router, which is able to monitor the traffic behavior, and change the buffer depth of each channel at runtime. Besides, the dynamic configuration of the buffer depth is done without any pause or interruption in the system. As applications show different traffic behavior at runtime, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was approximately 80% lower and throughput was increased 2 times, on average, for the same buffer depth. Moreover, the adaptive router allows up to 30% power savings, while maintain the same performance of the equivalent homogeneous router.

A Network-on-Chip with large FIFO size ensures performance during the execution of different traffic flow, but unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers to reach higher throughput incurs in extra dissipation for the mean case, which is much more frequent. In this paper we propose the use of an adaptive router with a mechanism that, using a flow sensor, verifies during run time the behavior of the data traffic. From the observability of the data flow, the system uses a control equation that adapts itself to provide an appropriate buffer depth for each channel to sustain performance with minimum power dissipation. As applications show different traffic behavior at run-time, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was 75% lower and throughput was increased 4.6 times to Xbox application, for the same buffer depth. Moreover, the adaptive router allows up to 28% power savings, while maintain the same performance of the equivalent homogeneous router.