Search

In this chapter, different GALS approaches for the implementation of embedded NoC architectures were presented. The GALS approach allows for the reduction of the resource requirements at an increased scalability of the NoC without sacrificing performance. The three approaches of synchronous, mesochronous, and asynchronous NoCs were compared. For the mesochronous NoC special synchronizers between the links were implemented. For the asynchronous NoC, the routers were completely realized as an asynchronous circuits. The results have shown that modern design methods (CCOpt design fl ow) allow a good scaling of MPSoCs even for synchronous NoCs. Nevertheless, the asynchronous NoC showed lower area and energy requirement compared to the mesochronous and synchronous implementation, while still providing a comparable performance. When comparing a place and route of an MPSoC, the asynchronous NoC leads to 3.1% less area requirements. The power consumption of an asynchronous router is only 22.4% (0.94 mW in idle state) or 53% (3.94 mW during communication) of the power consumption of a clock -based router. In the last section of the chapter, the global clock tree for an MPSoC with 256 CPUs was examined. The synchronous and mesochronous NoC show almost the same power consumption of about 7.7 mW. Using the asynchronous NoC reduces the power consumption by about 25% (5.78 mW). In addition, the mesochronous and asynchronous variants achieve a 2.6% higher clock frequency.

LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.

LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.