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The Booth multipliers require lower number of addition operations compared to the traditional multipliers. Further, higher radix Booth multiplier requires lesser number of adders in its circuit implementation. Multiply and accumulate (MAC) unit plays a crucial role in digital signal processing circuits. Handling the data in area-efficient MAC circuits is challenging since the data word length closely doubles on each multiplication. The data path of higher word length possesses higher hardware complexity. However, such hardware complexity can be minimized by deploying the fixed-width multipliers (FWM) in MAC circuits. In FWMs, the multiplication result of $${{X}_{L-\mathrm{bits}}}\times {{Y}_{L-\mathrm{bits}}}$$ is rounded to the higher significant L bits by truncating the rest of lower significant bits. Nevertheless, this truncation introduces the error in multiplication result. This paper presents a radix-8 Booth-based fixed-width signed multipliers with error compensation. Moreover, the estimation of bias value for the error compensation in radix-8 Booth FWM is presented. Accuracy of the fixed-width multiplication with the proposed compensation is analyzed. In addition, the multiplier circuits based on the proposed methods are designed and implemented and the experimental results are discussed.

The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi-user (MU) multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) technique is adopted for the high data rate communication. In an MIMO-OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On proper reception, the reordering and scheduling of data is important for the optimal utilisation of butterfly resources in the pipelined FFT/IFFT processor. In this study, a mathematical model for an eight-parallel multimode (N = 512/256/128/64) multi-path delay commutator-based FFT/IFFT processor which is suitable for the IEEE 802.11ac compliant MU-MIMO-OFDM system is presented. On the other hand, the data reordering, scheduling methodologies and its architectures are proposed for the pre-, post-FFT/IFFT process are proposed. The design implementations are done using TSMC 65 nm complementary metal–oxide–semiconductor technology at 160 MHz. The power and area metrics with and without clock gating are compared. The clock gated implementation reports show that the power consumption is 17.44 mW for the pre-transformed data reordering and 11.64 mW for the post-transformed data reordering with an area occupation of 0.7694 mm2 and 0.5111 mm2, respectively.

Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry Select Adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple carry adder (RCA) in the structure. To reduce the area of CSLA, a CSLA with Binary to Excess-1 Converter is already designed which reduces the area of adder. But there are other techniques to design a CSLA to reduce its area. One of such technique is using an add one circuit technique. This paper proposes the design of square root CSLA (SQRT CSLA) using add one circuit with significant reduction in area. The proposed design is synthesized using Leonardo Spectrum to get area (number of gates) and delay (ns). The performance in terms of area and delay are evaluated for square root CSLA using add one circuit and are compared with existing SQRT CSLA and SQRT CSLA using Binary to Excess-1 Converter (BEC). The results analysis shows that the proposed SQRT CSLA using add one circuit is better than the existing SQRT CSLA and SQRT CSLA using BEC.

Fingerprint recognition is one of the most popular methods used by Biometric identification systems for personnel identification. CORDIC algorithm provides wonderful solution to perform the math intensive operations at the cost of few components like adder, shifter, multiplexer.Etc. Such math intensive operations are required to perform during the image enhancement phase of finger print recognition process. In this paper CORDIC based architecture is proposed to evaluate almost all the trigonometric functions. This is implemented using XILINX ISE 13.2. Performance of the architecture is analyzed in terms of relative error.

Finger print recognition process involves many trigonometric evolutions. CORDIC based evolution of trigonometric functions is possible. In this paper CORDIC based architecture is proposed to evaluate the trigonometric or inverse trigonometric functions like sinθ, cosθ. Proposed architecture is partitioned into two main blocks: Magnitude generator and CORDIC processor. Magnitude generator outputs the value of the trigonometric function by driving the CORDIC processor. CORDIC processor executes the CORDIC rotations. Architecture Proposed in this paper is implemented using XILINX 13.2. Performance of the architecture is analyzed by calculating the relative error and resource utilization summery is reported.