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In this paper we show for the first time the possibility to direct grow and tune the size and optical properties of high quality InAs/GaAs quantum dots on transferable crystalline silicon nanomembranes. The transferable silicon nanomembranes have been grown via in-situ H2 prebake of porous silicon in Ultra High Vacuum Chemical vapour Deposition (UHV-CVD) reactor. Flat and continuous transferable crystalline nanomembranes with thicknesses below 30 nm have been obtained. The mechanical strain in the silicon nanomembranes has been tuned via sintering temperature between 900 and 1100 °C for the direct crystalline growth of transferable InAs/GaAs (QDs)/Si foils. The size and band gap energy of these InAs/GaAs quantum dots are tuned via strain engineering in silicon nanomembranes. Several advanced techniques such as Scanning Electron Microscopy (SEM), High-Resolution Transmission Electron Microscopy (HR-TEM), X-Ray Diffraction (XRD), Photoluminescence (PL) spectroscopy are used to investigate the structural and optical properties of transferable silicon nanomembranes and the grown InAs/GaAs QDs. High quality InAs/GaAs QDs with tuned sizes grown on flat and continuous transferable crystalline nanomembranes have been obtained. The obtained results have shown that this novel process allows the growth of well separated InAs/GaAs QDs with well defined shape, high density around 2 × 1010/cm2 and a well controlled size variation as function of the substrate strain between 2 and 10 nm. The high quality of the structural and optical properties of the InAs/GaAs QDs monolithically grown on a transferable Si nanomembranes and its compatibility with standard Si solar cells technologies offer a great opportunity for growing a cheap and high performance InAs/GaAs quantum dots/Si third generation solar cells and microelectronic devices.

In this paper, it is shown for the first time that Ge nanocrystals (Ge NCs) obtained via solid-state dewetting of amorphous GOI can be used as the active absorbers embedded in a silicon dioxide matrix of metal–insulator–semiconductor photodetectors (MIS PD). The Ge NCs have been obtained by a combination of Ge deposition by molecular beam epitaxy (MBE) on tunnel thermal silicon oxide and solid-state dewetting processes. The structural and morphology characterizations performed using high-resolution transmission electron microscopy (HRTEM) and scanning electron microscopy (SEM) show that the Ge NCs embedded in SiO2 of MIS PD are monocrystalline, homogeneous and have well-defined shape and high density suitable for optoelectronic applications. The I–V and photocurrent measurements performed on these innovative structures show that the Ge NCs contribute efficiently in the electrical transport by increasing the current density via creating an intermediate conduction step in the MIS structure and enhance the photocurrent via photogeneration of new carriers. We have observed that for the structure with Ge NCs, the photocurrent increases 10 times at reverse bias Vg = − 1 V when it is illuminated. These results indicate that the crystalline Ge NCs obtained via solid-state dewetting can be integrated with optoelectronics and photonics technologies to produce new high-performance optoelectronic devices fully compatible with complementary oxide metal (CMOS) technology.

We report self-assembled InAs/GaAs quantum dots (QDs) monolithically grown on a compliant transferable silicon nanomembrane. The transferable silicon nanomembrane with flat continuous crystalline silicon layer formed via in situ porous silicon sintering is considered a low-cost seed for heteroepitaxy of free-standing single-crystalline foils for photovoltaic cells. In this paper, the compliant feature of transferable silicon nanomembrane has been exploited for direct growth of high-quality InAs/GaAs (QDs) by molecular beam epitaxy. Bright 1.3 µm room temperature photoluminescence from InAs/GaAs QDs has been obtained. The excellent structural and optical qualities of the obtained InAs/GaAs quantum dots offer great opportunities for realizing a low-cost and large-scale integration of III–V-based optoelectronic device on silicon.

We report the high performances of Metal-Insulator-Semiconductor Photodetectors (MIS PD) made with crystalline Ge nanocrystals (Ge NCs) as the active absorbers embedded in a silicon dioxide matrix. The Ge NCs have been obtained by a combination of Ge deposition by Molecular Beam Epitaxy (MBE) on tunnel thermal silicon oxide and solid state dewetting processes. Ge NCs structure and morphology are characterized by High Resolution Transmission Electron Microscopy (HRTEM) and Scanning Electron Microscopy (SEM). The photocurrent generation is determined by I-V spectroscopy and Photocurrent spectroscopy. We evidence the role of high quality Ge NCs on photocurrent and explain the high sensitivity of MIS photodetector as a result of transport mechanisms via photoexcited Ge NCs.These results indicate that the crystalline Ge NCs obtained via solid state dewetting can be integrated with opto-electronics and photonics technologies to produce new high performance optoelectronic devices fully compatible with Complementary Oxide Metal (CMOS) technology.

In the present work, we report on the charge trapping properties of Germanium Nanocrystals (Ge NCs) self assembled on SiO2 thin layer for promising applications in next-generation non volatile memory by the means of Deep Level Transient Spectroscopy (DLTS) and high frequency C-V method. The Ge NCs were grown via dewetting phenomenon at solid state by Ultra-High Vacuum (UHV) annealing and passivated with silicon before SiO2 capping. The role of the surface passivation is to reduce the electrical defect density at the Ge NCs-SiO2 interface. The presence of the Ge NCs in the oxide of the MOS capacitors strongly affects the C-V characteristics and increases the accumulation capacitance, causes a negative flat band voltage (VFB) shift. The DLTS has been used to study the individual Ge NCs as a single point deep level defect in the oxide. DLTS reveals two main features: the first electron traps around 255 K could correspond to dangling bonds at the Si/SiO2 interface and the second, at high-temperature (>300 K) response, could be originated from minority carrier generation in Ge NCs.

Device structures with silicon or germanium nanodots embedded in an oxide matrix may find application in the field of Non-Volatile Memories (NVMs) [1,2] or photonics [3,4]. In the former case, the nanodots can become charged by tunneling of electrons or holes from the silicon substrate through a tunnel oxide. Successful operation requires that the charge does not leak away by the assistance of traps or defects in the material stack. The latter can be probed by techniques like Admittance Spectroscopy [5] or Deep-Level Transient Spectroscopy (DLTS) [2,5]. In the present work we report on a systematic investigation of Metal-Oxide-Semiconductor (MOS) capacitors fabricated on n-type Czochralski silicon substrates and containing Ge nanodots with different size. Ge nanodots with average diameter of 1, 2 or 3 nm have been deposited by Molecular Beam Epitaxy (MBE) on a 5 nm tunnel oxide, thermally grown on n-type Czochralski silicon wafers. An Atomic Force Microscopy (AFM) picture is shown in Fig. 1. Next, 50 nm of SiO2 is deposited. MOS capacitors are prepared by thermal evaporation of 2 mm diameter Al gate contacts, while InGa+In foil ohmic contacts are prepared on the silicon substrate side. The device structure is schematically shown in Fig. 2. Capacitance-Voltage (C-V) characterization is performed at a fixed frequency f=1 MHz, using both a forward and reverse gate voltage sweep. As can be seen in Fig. 3, the presence of the Ge nanodots has a pronounced impact on the C-V characteristics: there is a shift towards positive flat-band voltage, compared with the zero dot reference, a strong increase of the accumulation capacitance and, for the nanodot samples, the hysteresis increases with the increase in nanodot size. For temperature (T-) scan DLTS, the capacitors are mounted in a helium contact gas cryostat cooled with liquid nitrogen. Measurements at different bias pulses from reverse bias (VR) to the pulse bias (VP) are performed in parallel in order to probe the electron traps in different parts of the structure. An example is given in Fig. 4, for the 1 nm nanodots sample. It shows that in deep depletion, there is a broad peak between 150-250 K which could stem from the response of filled interface traps. The increase found at room temperature may originate from minority carrier generation in the depletion region [2,5,6]. When probing closer to the interface, for more positive VR, a pronounced but broad peak around 200 K dominates the spectra. From the Arrhenius plot shown in Fig. 5, it is concluded that it corresponds to the dangling bond (Pb) acceptor level at about 0.31 eV from the conduction band [2,5,6]. Maximum densities are estimated in the range of 5x1011 cm-2eV-1. A comparison of the spectra near the interface for the different samples studied is provided in Fig. 6 and will be discussed in more detail in the conference paper. References [1] S. Tiwari, H. Hanafi, A. Hartstein, E.F. Crabbe and K. Chan, Appl. Phys. Lett., 68, 1377 (1996). [2] R. Beyer, J. von Borany and H. Burghardt, Microelectron. Eng., 86, 1859 (2009). [3] J. von Borany, R. Grötzschel, K.H. Heinig, A. Markwitz, W. Matz, B. Schmidt and W. Skorupa, Appl. Phys. Lett., 71, 3215 (1997). [4] D.A. Grachev, A.V. Ershov, A.V. Belolipetsky, L.V. Krasilnikova, A.N. Yablonskiy, B.A. Andreev and O.B. Gusev, Phys. Stat. Sol. A, 213, 2867 (2016). [5] E. Simoen, J. Lauwaert and H. Vrielinck, Semiconductors and Semimetals, Eds. L. Romano, V. Privitera and C. Jagadish, 91, pp. 205-250, Elsevier 2015. [6] S.N. Volkos, E.S. Efthymiou, S. Bernardini, I.D. Hawkins, A.R. Peaker and G. Petkos, J. Appl. Phys., 100, 124103 (2006). Figure 1

The dual action of oxide-related defects in the visible and infrared emission of germanium (Ge) self-assembled quantum dots (QDs) is discussed. The Ge particles were fabricated by solid-state dewetting on a thin layer of $${\hbox {SiO}}_{2}$$ . Subsequent surface passivation by amorphous silicon was carried out for several samples. All samples were encapsulated by $${\hbox {SiO}}_{2}$$ . Atomic force microscopy analysis indicates a linear relationship between the size of QDs and the initial thickness of the amorphous Ge films. The crystallization of the QDs was evidenced by transmission electron microscopy and Raman spectroscopy. Photoluminescence measurements show that the main visible emission is blue-green centred around 520 nm. The luminescence attributed to the radiative recombination of quantum-confined excitons is only observed when the surface is in-situ passivated prior to the deposition of the oxide matrix. The results of this work are helpful for optimizing the performance of the optoelectronic devices based on the infrared emission of Ge nanocrystals.

International audience; In this study, we demonstrate a completely novel synthesis route for producing magnetic porous silicon. The magnetic properties of this material are induced by manganese atoms. The Mn-doping in Si is achieved by ion implantation. A subsequent anodization of the substrate is done to turn it into porous silicon. Several characterization techniques, such as transmission electronic microscopy, atomic force microscopy and photoluminescence are combined to probe the structural and the optical properties of this material. Furthermore, temperature and magnetic field dependent magnetization is analyzed using superconducting quantum interference device. In addition to the well-reported structural and optical properties of the porous silicon, our Mn-doped porous silicon samples exhibit a magnetic behavior with a curie temperature (T-C) higher than room temperature. These results indicate that the magnetic porous silicon can be integrated with microelectronics and photonics technologies to produce new devices, such as magnetophotonic crystals and polarized emitting diodes.

International audience; Single crystal Silicon (Si) layers have been deposited by molecular beam epitaxy on double-layer porous silicon (PSi). We show that a top thin layer with a low porosity is used as a seed layer for epitaxial growth. While, the underlying higher porosity layer is used as an easily detectable etch stop layer. The morphology and structure of epitaxial Si layer grown on the double-layer PSi are investigated by high resolution X-ray diffraction and transmission electron microscopy. The results show that, an epitaxial Si layer with a low defect density can be grown. Epitaxial growth of thin crystalline layers on double-layer PSi can provide opportunities for silicon-on-insulator applications and Si-based solar cells provided that the epitaxial layer has a sufficient crystallographic quality.

Direct laser reshaping of nanostructures is a cost-effective and fast approach to create or tune various designs for nanophotonics. However, the narrow range of required laser parameters along with the lack of in-situ temperature control during the nanostructure reshaping process limits its reproducibility and performance. Here, we present an approach for direct laser nanostructure reshaping with simultaneous temperature control. We employ thermally sensitive Raman spectroscopy during local laser melting of silicon pillar arrays prepared by self-assembly microsphere lithography. Our approach allows establishing the reshaping threshold of an individual nanostructure, resulting in clean laser processing without overheating of the surrounding area.

International audience; The growth of heteroepitaxial planar fully strained SiGe layers with high Ge concentration and large thickness enables tailoring electronic properties for enhanced transport properties and photoemission. We give here the first experimental and theoretical proof that high temperature flashed porous silicon layers (HT-PSi) perfectly accommodate the stress of SiGe layers and provide compliant substrates with unprecedented capabilities for the fabrication of planar SiGe nanomembranes. We show that the stress driven morphological evolution leading to self-organized quantum dots commonly observed on nominal Si (001) is fully inhibited when growing SiGe on such a HT-PSi substrate. The elastic behavior of HT-PSi results from two specific features: It is ten times softer than Si and tensily strained. Theoretical analysis proves that the compliant behavior of HT-PSi is due to the strain effect, while on the contrary its elastic softness favors the development of 3D growth. The inhibition due to the tensile strain produces atomically flat layers free of misfit dislocation.

International audience; Thick porous silicon (PS) buffer layers are used as sacrificial layers to epitaxially grow planar and fully relaxed Ge membranes. The single crystal Ge layers have been deposited by molecular beam epitaxy (MBE) on PS substrate. During deposition, the pore network of PS layers has been filled with Ge. We investigate the structure and morphology of PS as fabricated and after annealing at various temperatures. We show that the PS crystalline lattice is distorted and expanded in the direction perpendicular to the substrate plane due to the presence of chemisorbed –OH. An annealing at high temperature (> 500 °C), greatly changes the PS morphology and structure. This change is marked by an increase of the pore diameter while the lattice parameter becomes tensily strained in the plane (compressed in the direction perpendicular). The morphology and structure of Ge layers are investigated by transmission electron microscopy, high resolution X-ray diffraction and atomic force microscopy as a function of the deposition temperature and deposited thickness. The results show that the surface roughness, level of relaxation and Si-Ge intermixing (Ge content) depend on the growth temperature and deposited thickness. Two sub-layers are distinguished: the layer incorporated inside the PS pores (high level of intermixing) and the layer on top of the PS surface (low level of intermixing). When deposited at temperature > 500 °C, the Ge layers are fully relaxed with a top Si1 − xGex layer x = 0.74 and a very flat surface. Such layer can serve as fully relaxed ultra-thin SiGe pseudo-substrate with high Ge content. The epitaxy of Ge on sacrificial soft PS pseudo-substrate in the experimental conditions described here provides an easy way to fabricate fully relaxed SiGe pseudo-substrates. Moreover, Ge thin films epitaxially deposited by MBE on PS could be used as relaxed pseudo-substrate in conventional microelectronic technology.

International audience; We demonstrate that perfectly reproducible and homogeneous core-shell Si1−xGex/Ge nanowires can be produced by a two step nanofabrication process. The process makes use of a combination of Liquid Metal Alloy Ion Source–Focused Ion Beam (LMAIS-FIB) nanomilling and condensation. In a first step, we fabricate arrays of SiGe wires by LMAIS-FIB milling of fully relaxed Si1−xGex pseudo-substrates. The use of Ge2+ ions during this step avoids any metallic contamination of the nanowires. In a second step, we both reduce the diameter of the wires and form the core-shell configuration by oxido-reduction of the wires. Large arrays of core-shell nanowires with extended aspect ratio (length over diameter), small diameters and ultra-thin shell thickness are fabricated. Multilayer core-shell configurations with tunable arrangements could also be produced by repeated condensation cycles.

International audience; Porous silicon (PSi) layers are used as templates to grow epitaxial planar and fully relaxed Ge pseudo-substrates. An annealing at 600 °C, dramatically changes the PSi morphology and produces compliant template layers which serve in a second step, as substrate for the epitaxy of fully relaxed SiGe layers with a Ge content between 50% and 94%. The SiGe pseudo-substrates produced by such process exhibit a remarkable planar surface resulting from the penetration of Ge inside the pores. They could be integrated into conventional microelectronic technology for the subsequent deposition of active layers such as tensily strained Si or relaxed Ge.