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The study identifies barriers to participation in cruises from domestic homeports among higher income Chinese adults. Results from 775 respondents extend leisure constraints theory by revealing that “structural” constraints (lack of knowledge, time, and money) most influence intentions not to cruise even for these wealthier consumers, whereas “not‐an‐option” constraints (disinterest due to previous cruising experience, intentions to cruise from a foreign homeport) are least influential. “Personal” factors (lack of companions and fears about safety, boredom, and seasickness) are moderately important. Six identified clusters include a large normative “moderate‐constraint” cluster, small “low‐potential” and “high‐potential” segments, and several specialized segments.

This paper proposed the high-frequency, multi-harmonic-controlled, Class-F power amplifier (PA) implemented with 0.5 μm GaN Hetrojunction Electron Mobility Transistor (HEMT). For PA design at high frequencies, parasitics of a transistor significantly increase the difficulty of harmonic manipulation, compared to low-frequency cases. To overcome this issue, we propose a novel design methodology based on a band-reject, low-pass, output matching network, which is realized with passive components. This network provides optimal fundamental impedance and allows harmonic control up to the third order to enable an efficient Class-F behavior. The implemented PA exhibits performance at 2.5 GHz with a 50% PAE, 14 dB gain, and 10 W output power.

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.

PurposeThe purpose of this study is to analyse factors influencing subscribers' usage of 3G mobile services in Taiwan.Design/methodology/approachThe research model, based on a technology acceptance model (TAM) and added perceived enjoyment, was tested by means of a two‐stage structure equation modelling approach. Data were collected from 532 respondents via a web questionnaire survey.FindingsThe findings indicate that perceived usefulness, perceived ease of use and perceived enjoyment are positively related to attitude, and perceived enjoyment has a positive influence on perceived usefulness.Practical implicationsThe findings suggest users of 3G mobile services need to be provided with more diverse and entertaining ways of communicating, which are at the same time easily accessible and convenient to use.Originality/valueA new correlation from perceived enjoyment to perceived usefulness was found to have a significant effect. This finding indicates enjoyment as a key factor influences customers' adoption of 3G services.

The enhancement-mode (E-mode) and depletion-mode (D-mode) device operations on the same chip and their monolithic integration to form a DCFL inverter by using the double δ-doped AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors have been successfully fabricated and investigated. Distinguished static and microwave-frequency characteristics of the E-mode and D-mode pHEMTs at high ambient temperatures and the temperature-dependent performances of the monolithic DCFL gate integration have been comprehensively studied. Experimentally, the studied device demonstrates superiorly stable thermal threshold coefficient (∂Vth/∂T) of 1 (−1.27) mV/mm-K for the D-mode (E-mode) device. The noise margins of the DCFL inverter, at VDD = 1 V, are superiorly maintained above 0.1 V as the ambient temperature increases up to 400 K. The present devices are promisingly suitable for the low-power-dissipation, high-temperature digital circuit or the mixed-mode circuit applications.

Various static and microwave performances on InAlAs/InGaAs/InP HEMTs with a linearly-graded InxGa1−xAs channel (LGC-HEMT) have been comprehensively investigated and compared to those having a conventional lattice-matched In0.53Ga0.47As channel (LM-HEMT). Improved carrier transport characteristics and confinement capability by employing the linearly-graded channel have contributed to superior extrinsic transconductance (gm) of 346 mS mm−1, gate-voltage swing (GVS) of 0.5 V (182 mA), unity-gain cut-off frequency (ft) of 41 GHz and maximum oscillation frequency (fmax) of 63 GHz, with an improved frequency operation plateau at 300 K for a gate dimension of 0.65 × 200 µm2. Furthermore, improved kink effects leading to a lower gate leakage current of 0.7 µA mm−1, lower output conductance (gd) of 3.6 mS mm−1, higher voltage gain (AV) of 93.1, higher off-state breakdown voltage of 16.3 V and superior output power characteristics have also been discussed.

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP/sub 3/) of -5.01 dBm, and IIP/sub 3//dc of -6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.

In this paper, a bit weight extraction technique is proposed to test and calibrate the successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique is based on major carrier transition (MCT) testing, the MCTs are generated through simple capacitor switching and then measured by the embedded comparator and a coarse design-for-test (DfT) digital-to-analog converter (DAC) that couples to the capacitor DAC (CDAC). From the results, the individual bit weights are extracted and the ADC performance can thus be estimated and calibrated. Simulation results show very high test accuracy and linearity improvement can be achieved by the proposed technique.

A discrete-time charge-domain filter (CDF) with bandwidth calibration was proposed for LTE application. The CDF, based on feedback gain and delay, could suppress sinc distortion to achieve a like brick-wall filtering. Moreover, CDF with non-decimation and multi-stage topology could overcome the noise-folding issue and save chip area. The measurement showed that CDF performed a >59dB adjacent channel rejection (ACR), >85dB stop-band attenuation, and 5-to-26 MHz reconfigurable bandwidth. The chip also possessed 41dB conversion gain under 7mA current from a 1.2V power supply. The chip, including whole CDF and clock circuits, occupies 0.52mm2 in 65nm CMOS process.

A quadrature charge-domain filter (QCDF) for frequency down-conversion and filtering is proposed. After measurement of QCDF by a 1072-MS/s sampling rate, a stop-band attenuation and bandwidth were 53-dB and 44-MHz, respectively. For quadrature performance after down-conversion, this QCDF provided −27.67-dB EVM upon a 64-QAM signal with 54-Mb/s. This chip consumed 7.7-mA power current upon a 1.2-V supply and occupied 0.08-mm 2 in 90-nm CMOS process.

Integration of a programmable-bandwidth front-end (PBFE) based on clock-interleaving down-conversion filter (CIDCF) is presented. After demonstration, PBFE has a programmable bandwidth from 1-MHz to 110-MHz. Under 6.14-mA power current (excluding output buffer) and 1.2-V power supply, PBFE gets +8.2-dBm IIP3, +45-dBm IIP2, and 2.6-dB gain. Moreover, a better than 26.79-dB alias-band rejection and 34.032-dB image rejection ratio are obtained. Using a 64-QAM signal with 54-MS/s for IEEE 802.11g standard, PBFE achieves -26.351-dB EVM on a 2.412-GHz RF frequency, 1.072-GHz LO frequency, and 1072-MS/s sampling frequency.

A 5.25-GHz CMOS even harmonic mixer (EHM) using a dual Class-AB circuit is presented. The dual Class-AB circuit in the RF stage can improve the linearity and conversion gain for wireless receivers. In addition, the dual Class-AB circuit adjusting the mixing power from the frequency-doubling circuit can overcome the process variation. After an implemented chip, the measurement reveals that the proposed EHM has a power consumption of 4.13-mW, conversion gain of 13.133-dB, IIP3 of ?1.033-dBm, and IIP2 of 48.267-dBm under the LO frequency of 2.623-GHz. With a measured linearity upon a high power conversion gain, the proposed EHM shows improved performance compared with other published active EHMs.

This paper proposes a 5.25 GHz folded-cascode even harmonic mixer (FEHM) for low voltage applications. This FEHM adopts the folded technique to reduce the headroom voltage, employs current reuse circuit to improve linearity, and uses double frequency technique to overcome the DC offset problem for direct conversion receivers. At an IF frequency of 500 kHz, the measurement reveals that the proposed FEHM possesses conversion gain of 8.89 dB, IIP3 of -11.555 dBm, and IIP2 of 17.32 dBm under supply voltage of 0.9 V with power consumption about 6.57 mW

A 1-V low-power 2.4-GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 /spl mu/m CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using a dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigma-delta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. Simulation results show the synthesizer possesses a tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1 MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm/sup 2/, and the total power consumption is 8.94 mW.

A 5.25 GHz CMOS even harmonic mixer (EHM) with an enhancing inductance is implemented in a TSMC 0.18 /spl mu/m CMOS process for extra low power direct conversion receivers. In the proposed EHM, a current reuse pair, a double frequency circuit, and an enhancing inductance are employed in promoting the mixer performance, such as conversion gain, linearity, and noise figure. Moreover, measurement results reveal that the proposed EHM, under a supply voltage of 1.8 V and an LO frequency of 2.62 GHz, possesses a power consumption of 0.666 mW, with linear efficiency (IIP/sub 3//DC) of -16.15 dB, and 0.936 mW, with IIP/sub 3//DC of -8.13 dB, at high gain mode and high linear mode, respectively.

A topology for even harmonic mixer (EHM) is presented. This proposed mixer employs a current reuse circuit and a double frequency technique to improve the linearity and isolation problems, respectively. Moreover, theoretical analyses for conversion gain, 1-dB compression point, and 3rd-order intermodulation point as functions of the circuit bias and technology parameters are derived by Taylor series expansion with short channel current model and verified by experimental data. The measured results reveal that the proposed mixer possesses single-end conversion gain of 9.17 dB, third-order input intercept point (IIP3 ) of -5.01 dBm, IIP3/DC of 23.69 dBm, and the 2LO-IF and 2LO-RF isolations of 75 dB and 58.33 dB, respectively, under supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs current reuse and double frequency circuits in the RF input stage and LO stage, respectively, to improve its linearity and isolation. In addition, the proposed topology has the advantage of the low power consumption. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of conversion gain and linearity have been described in details. The measured results reveal that the proposed mixer possesses single-end conversion gain of 8 dB and third-order input intercept point (IIP3) of --3.8 dBm, respectively, under the supply voltage of 1.8 V and LO power of 4 dBm. The power consumption of the proposed mixer is about 1.4 mW at 900 MHz.