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The NROM-cell concept is introduced as a promising technology for replacing Flash nonvolatile memory devices also in embedded products, owing to its intrinsic 2-b/cell operation and better endurance. This method has allowed profiling hole distribution in devices erased with different bias conditions and also monitoring the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

The investigation of reliability of actual flash memory technologies and prediction of future trends is discussed through the use of a recently proposed statistical model of stress-induced leakage current. The effects of tunnel oxide scale on flash memory data retention requirements are predicted.

The physical mechanism of NROM memory erase is investigated. Results reveal that the hot-hole injection will be identified as the actual conduction mechanism of NROM erases, and two compact models capable of describing the main characteristics of NROM, erase current will be developed.

The NROM cell consists of an n-channel MOSFET in which the gate dielectric replaced with a silicon nitride layer pressed between two silicon dioxide layers. By means of drift-diffusion simulations, effects of nitride charge on NROM transcharacteristics have been studied.

A new floating gate memory cell model suitable for circuit simulation is developed that is capable to correctly simulate the electrical behaviour of the memory cell in every bias behaviour. This model features many advantages over the previous ones and is easy and simple to implement.

Capacitive-coupling coefficient dependence on bias and W/L is examined, and classic methods to extract values from electrical characterizations are reviewed. results obtained from a new model are compared to classic values.

Research has established a novel technique to estimate charge injection and hot carrier effects in self-aligned, etched-polysilicon, npn bipolar transistors with silicon dioxide sidewall emitter spaces. The method estimates maximum electric field changes in the base-emitter junction space charge region at the silicon/sidewall oxide interface.

A survey of hot electron effects occurring in low current density-operated AlGaAs/GaAs heterojunction bipolar transistors provides accurate characterization of impact ionization effects. It uses Monte Carlo simulations to model the carrier distribution functions. Measurements of the base current changes give an estimate of impact ionization whereas simulations demonstrate the influence of dead-space effects on the device multiplication factor. Simulations optimize the collector composition and doping profile, and provide a way out of the breakdown-speed dilemma.

Impact-ionization effects' measurements in bipolar transistors are characterized. Impact ionization has an effect on the base resistance of the current and voltages applied to the device. A dc method for the extraction of all inhibiting resistances in bipolar transistors at the same time is also presented.

In this paper we describe a simulator which can be used to study the effects on circuit behavior of two radiation phenomena: Single Event Upset (SEU) and total-dose radiation effects. Using this simulator the user can predict the error rate in large circuits due to single event upset. The error rate model described here uses a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for very complex circuits. The simulator predicts circuit behavior after total-dose irradiation using as inputs: the dose rate and the total dose parameter sets that characterize the transistor response to radiation, and the circuit netlist. The total-dose simulator is based on physical models of the changes in the MOSFET caused by radiation. We quantify the degradation of each MOSFET in a circuit with two parameters and determine the change in the MOSFET characteristics from preirradiation MOSFET data. Using the 'irradiated' MOSFET parameters, we can simulate circuit behavior using an ordinary circuit simulator such as SPICE. With this simulator, one can study how resistant a circuit is to changes due to irradiation and design circuits to be functionally radiation 'hard'. The 'double-kink' in the MOSFET subthreshold region due to the parasitic effect of the edge transistors can be simulated and the user is advised when leakage current is unacceptably large. The speed degradation of a ring oscillator was simulated and the results compared with actual measured data.

Studies on a nonlocal analytical model for the avalanche multiplication factor reveal that the model simulates impact-ionization-induced snap lack for an Si n-p-n BJT at constant emitter-base voltage. The model includes the base parasitic resistance's bias-dependent value. The model assumes a triangular electric field and calculates electron average energy in the base collection domain.

Efforts to extract MOS parameters are reported using a new model of gate capacitance.