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As a novel similarity measure that is defined as the expectation of a kernel function between two random variables, correntropy has been successfully applied in robust machine learning and signal processing to combat large outliers. The kernel function in correntropy is usually a zero-mean Gaussian kernel. In a recent work, the concept of mixture correntropy (MC) was proposed to improve the learning performance, where the kernel function is a mixture Gaussian kernel, namely, a linear combination of several zero-mean Gaussian kernels with different widths. In both correntropy and MC, the center of the kernel function is, however, always located at zero. In the present work, to further improve the learning performance, we propose the concept of multikernel correntropy (MKC), in which each component of the mixture Gaussian kernel can be centered at a different location. The properties of the MKC are investigated and an efficient approach is proposed to determine the free parameters in MKC. Experimental results show that the learning algorithms under the maximum MKC criterion (MMKCC) can outperform those under the original maximum correntropy criterion (MCC) and the maximum MC criterion (MMCC).

The rapid increase of wearable sensor devices poses new challenges for implementing continuous real-time processing of physiological data. Neuromorphic sensory-processing devices can enable both the measurement of bio-signals and their processing locally in compact embedded wearable systems. In particular, mixed-signal spiking neural networks implemented on neuromorphic processors can be integrated directly with the sensors to extract temporal data-streams in real-time with very low power consumption. In this work, we present a neuromorphic approach for classifying spatio-temporal data from electromyography (EMG) signals, which paves the way toward the realization of compact wearable solutions for neuroprosthetic control. Here we extend previously proposed delta-encoding methods to transform bio-signals into spike trains and use a spiking Recurrent Neural Network (SRNN) architecture to extract features from them. The SRNN was first simulated in software to find the optimal set of hyperparameters, and then validated on the neuromorphic hardware, with a difference in the performance of less than 2%. We describe how biologically plausible mechanisms such as Spike-Timing Dependent Plasticity (STDP) and soft Winner-Take-All (WTA) networks can be exploited to classify the EMG signals and show how their combined use in EMG data classification achieves competitive results with different datasets. Specifically, the classification performance for the Roshambo EMG dataset, which has three different classes, is above 85%, and for the basic finger movements dataset from the Ninapro database, which has eight different classes, reaches 55% accuracy.

Video display processing is an indispensable module in a variety of multimedia systems. With the increase of video format to 4K $\times$ 2K@60fps, the design of efficient display processing circuit faces severe challenges. This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced algorithms for perpetual image quality improvement. By leveraging algorithm and architecture co-design, this paper efficiently implements these computational and memory intensive display processing algorithms in a single chip. In particular, we describe three representative design modules in detail, including motion compensated frame rate up-conversion, content-adaptive contrast enhancement, and backlight local dimming. Extensive experiments demonstrate that the proposed design modules outperform the previous works in terms of either image quality or hardware efficiency. The overall chip is fabricated in GF 55nm CMOS technology, and can work at the maximum operating frequency of 594 MHz. The maximum input and output video formats reach up to 4K $\times$ 2K@60fps.

Perturbation has a positive effect, as it contributes to the stability of neural systems through adaptation and robustness. For example, deep reinforcement learning generally engages in exploratory behavior by injecting noise into the action space and network parameters. It can consistently increase the agent's exploration ability and lead to richer sets of behaviors. Evolutionary strategies also apply parameter perturbations, which makes network architecture robust and diverse. Our main concern is whether the notion of synaptic perturbation introduced in a spiking neural network (SNN) is biologically relevant or if novel frameworks and components are desired to account for the perturbation properties of artificial neural systems. In this work, we first review part of the locality-sensitive hashing (LSH) of similarity search, the FLY algorithm, as recently published in Science, and propose an improved architecture, time-shifted spiking LSH (TS-SLSH), with the consideration of temporal perturbations of the firing moments of spike pulses. Experiment results show promising performance of the proposed method and demonstrate its generality to various spiking neuron models. Therefore, we expect temporal perturbation to play an active role in SNN performance.

Wearable sensor devices are disrupting healthcare technologies with a rapid increase of systems able to perform continuous monitoring of physiological data. These systems however typically produce large amounts of data that needs to be processed in real-time. Neuromorphic processors represent a promising class of devices that can be directly interfaced with the sensors to extract temporal data-streams in real-time with very low-power consumption. In this paper we present an application of such a neuromorphic approach for classifying electromyography (EMG) signals, that can be useful for designing compact wearable solutions for neuroprosthetic control. As the neuromorphic processor comprises configurable spiking neurons and adaptive synapses, we propose to use a spiking recurrent neural network (SRNN) for classifying the spatio-temporal data derived from the EMG signals. We performed a thorough investigation on the performance of the network implemented on the chip, by evaluating the classification performance of two hardware-friendly spike-based read-out models: a rate-based state distance model, and a spiking-time-dependent plasticity (STDP) learning model. The results were then compared with a classical machine learning approach based on the Support Vector Machine (SVM) method. Our results show how the classification accuracy of the state distance method is above 75%, which is even better than the SVM results; while the STDP learning rule only achieved 60% accuracy.

Keypoint-based detectors have achieved pretty-well performance. However, incorrect keypoint matching is still widespread and greatly affects the performance of the detector. In this paper, we propose CentripetalNet which uses centripetal shift to pair corner keypoints from the same instance. CentripetalNet predicts the position and the centripetal shift of the corner points and matches corners whose shifted results are aligned. Combining position information, our approach matches corner points more accurately than the conventional embedding approaches do. Corner pooling extracts information inside the bounding boxes onto the border. To make this information more aware at the corners, we design a cross-star deformable convolution network to conduct feature adaption. Furthermore, we explore instance segmentation on anchor-free detectors by equipping our CentripetalNet with a mask prediction module. On MS-COCO test-dev, our CentripetalNet not only outperforms all existing anchor-free detectors with an AP of 48.0% but also achieves comparable performance to the state-of-the-art instance segmentation approaches with a 40.2% MaskAP. Code will be available at https://github.com/KiveeDong/CentripetalNet., Accepted by CVPR2020

Spikes are the basic elements of information dissemination in the organic brain. A spike train, a series of discrete action potentials, incorporates the conception of time. Nowadays, the majority of existing artificial neural networks use numerical information to realize machine learning and cognition tasks. The advantage of numerical computation is its precision and remarkable performance on well-structured problems. However, cognition tasks have semi-structured or ill-structured information, even worse, some cannot reach a conclusion. According to biological experiments, the spiking neuron model is potentially more suitable for dealing with undetermined and unstructured problems. Researchers are trying to decode functional magnetic resonance imaging (fMRI) data, and this is a typical task to extract meaningful information from relatively undetermined and unstructured data. In this paper, we selected the Tempotron neuron model to analyze and reconstruct visual images from fMRI data when subjects received several kinds of visual stimuli; the preliminary results of pattern reconstruction were unpolished, but somewhat effective. Thus, a new structure for the spiking neural network was built to achieve better results. Several important aspects of the proposed model were discussed in this paper: the encoding of external stimulating signals, the extraction of effective features, the relative position of spike trains on the timeline, the back propagation of error, and the rationality of parameter selection. These aspects are crucial in the spiking neuron model’s implementation, and are worth further investigation in future studies.

Facing the challenge of processes in direct coal liquefaction (DCL), it is vital to develop optimal hydrogen-donor solvent (H-donor) to dramatically moderate coal liquefaction conditions. Here, we propose an approach for rational design of optimal H-donor candidates based on density functional theory (DFT) calculations combining reverse searching algorithm. First, the mechanism of hydrogen transfer from H-donor to coal radical was investigated by using common model compounds. DFT calculations show that the concerted hydrogen transfer route promoted by coal radicals is the dominant pathway. The C–H bond dissociation enthalpies (BDEs) show strong correlation with intrinsic reaction barriers and rate constants (in log scale), which allow us to define a cheap metric for comparing the hydrogen-donation ability of different H-donors. Then the framework for rational design of H-donor candidates is established to seek molecules with low C–H BDEs based on inverse molecular design strategy. In the searching procedu...

Human information processing depends mainly on billions of neurons which constitute a complex neural network, and the information is transmitted in the form of neural spikes. In this paper, we propose a spiking neural network (SNN), named MD-SNN, with three key features: (1) using receptive field to encode spike trains from images; (2) randomly selecting partial spikes as inputs for each neuron to approach the absolute refractory period of the neuron; (3) using groups of neurons to make decisions. We test MD-SNN on the MNIST data set of handwritten digits, and results demonstrate that: (1) Different sizes of receptive fields influence classification results significantly. (2) Considering the neuronal refractory period in the SNN model, increasing the number of neurons in the learning layer could greatly reduce the training time, effectively reduce the probability of over-fitting, and improve the accuracy by 8.77%. (3) Compared with other SNN methods, MD-SNN achieves a better classification; compared with the convolution neural network, MD-SNN maintains flip and rotation invariance (the accuracy can remain at 90.44% on the test set), and it is more suitable for small sample learning (the accuracy can reach 80.15% for 1000 training samples, which is 7.8 times that of CNN).

In this brief, we present an efficient architecture for multiview 3-D television (3DTV) processing. The architecture, which is designed for 4/8/9/16-compatible multiview 1080p and 4K displays, includes a frame memory controller, a parallel video scaling engine, and a subpixel rearrangement module for slanted lenticular displays. First, we observe and leverage computation locality in the viewpoint scaling problem, significantly reducing area and power overheads. Next, we propose an approximate formulation of the subpixel rearrangement computation, trading substantial computation energy for a small and analytically bounded error. Finally, we design a distributed data placement scheme that takes advantage of the inherent structured parallelism to amortize the cost of DRAM precharge cycles. Our proof-of-concept field-programmable gate array (FPGA) implementation is capable of processing frame-compatible streams in 1080p at 60 Hz and 4K at 30 Hz. Overall, the proposed optimizations lower the area by 2.75 $\times$ for our FPGA implementation, and both area and power by 3.5 $\times$ for an ASIC implementation.

The widespread use of synthetic polymers has made microplastic (MP) a new type of contaminant that has attracted worldwide attention. Studies have shown that wastewater treatment plants (WWTPs) are an important source of MP collection in the natural environment. This study investigated the removal efficiency and migration characteristics of MPs by sampling the sewage from each treatment section of a WWTP in Zhengzhou, China. The results showed that the abundance of MPs in the influent water and primary, secondary, and tertiary treatment discharges was 16.0, 10.3, 4.5, and 2.9 MP/L, respectively, and the total removal rate of MPs from the influent to the final effluent reached 81.9%. The MPs in the WWTP were mainly small-sized (0.08-0.55 mm), followed by medium-sized (0.55-1.7 mm). Fibers were the dominant MP shape in both the water and sediment samples. Black (36%) and red (23%) were the dominant MP colors. Six different polymer types of MPs were detected, which were mainly polypropylene followed by polyethylene. In general, for the MPs in the WWTP, the removal rate of fragments can reach 97.08%, which is better than that of fibers (70.50%); the removal rate of small-sized can reach 95.86%, which is better than that of medium-sized (83.53%) and large-sized (70.00%). In this study, primary treatment has better effects in eliminating fragments and large-sized MPs; secondary treatment has better effects in eliminating fibers and small-sized MPs. Although WWTPs have a very good removal effect on MPs, 870 million MP/d are still discharged into nearby rivers from WWTPs with a treatment scale of 300,000 m3/day. Graphical Abstract.

Semantic SLAM is an important field in autonomous driving and intelligent agents, which can enable robots to achieve high-level navigation tasks, obtain simple cognition or reasoning ability and achieve language-based human-robot-interaction. In this paper, we built a system to creat a semantic 3D map by combining 3D point cloud from ORB SLAM with semantic segmentation information from Convolutional Neural Network model PSPNet-101 for large-scale environments. Besides, a new dataset for KITTI sequences has been built, which contains the GPS information and labels of landmarks from Google Map in related streets of the sequences. Moreover, we find a way to associate the real-world landmark with point cloud map and built a topological map based on semantic map., Comment: Accepted by 2019 China Symposium on Cognitive Computing and Hybrid Intelligence(CCHI'19)

Routing algorithm design for on-chip networks (OCNs) has become increasingly challenging due to high levels of integration and complexity of modern systems-on-chip (SoCs). The inherent unreliability of components, embedded oversized IP blocks, and fine-grained voltage-frequency islands (VFIs) management among others, raise several challenges in OCNs: (a) network topologies become irregular or asymmetric making circular route dependencies that lead to deadlock hard to detect; and (b) routing algorithms that lack strong load-balancing properties often saturate prematurely. In order to address the aforementioned deadlock and load-balancing problems, we propose the traffic balancing oblivious routing (TBOR) algorithm. It is a two-phase routing algorithm consisting of: (1) construction of the weighted acyclic channel dependency graph (CDG) for the OCN to efficiently maximize available resource utilization; and (2) channel ordering across turn models to keep the underlying CDG cycle-free to guarantee deadlock-freedom using one or more turn-models. Channel bandwidth utilization and traffic balancing are achieved through static virtual channel allocation according to residual bandwidth of healthy links. In addition, we introduce in this work two schemes of different granularity of fault detection and analysis while guaranteeing in-order packet delivery by assigning a unique path to each flow. Extensive experiments demonstrate the proposed routing methodology outperforms previous algorithms.

To improve the reliability of on-chip network based systems, we design a deadlock-free routing technique that is more resilient to component failures and guarantees a higher degree of node connectivity. The routing methodology consists of three key steps. First, we determine the maximal connected subgraph of the faulty network by checking whether the defective components happen to be the cut vertices and bridges of the network topology. A precise fault diagnosis mechanism is used to identify partial defective routers. Second, we construct an acyclic channel dependency graph that breaks all cycles and preserves connectivity of the maximal connected subgraph . This is done through the cycle-breaking and connectivity guaranteed (CBCG) algorithm. Finally, we introduce a fault-tolerant adaptive routing scheme that can be used with or without virtual channels for network congestion avoidance and high-throughput routing. The simulation results show both the effectiveness and robustness of the proposed approach. For an $8 \times 8$ 2D-Mesh with 40 percent of link damage, full connectivity and deadlock freedom are still archived without disabling any faultless router in 98.18 percent of the simulations. In a 2D-Torus, the simulation percentage is even higher (99.93 percent). The hardware overhead for supporting the introduced features is minimal. An on-line implementation of cbcg using TSMC 65nm library has only 0.966 and 1.139 percent area overhead for the $8\times8$ and $16 \times 16$ 2D-Meshes.

Machine learning inspired potentials continue to improve the ability for predicting structures of materials. However, many challenges still exist, particularly when calculating structures of disordered systems. These challenges are primarily due to the rapidly increasing dimensionality of the feature-vector space which in most machine-learning algorithms is dependent on the size of the structure. In this article, we present a feature-engineered approach that establishes a set of principles for representing potentials of physical structures (crystals, molecules, and clusters) in a feature space rather than a physically motivated space. Our goal in this work is to define guiding principles that optimize information storage of the physical parameters within the feature representations. In this manner, we focus on keeping the dimensionality of the feature space independent of the number of atoms in the structure. Our Structural Information Filtered Features (SIFF) potential represents structures by utilizing a feature vector of low-correlated descriptors, which correspondingly maximizes information within the descriptor. We present results of our SIFF potential on datasets composed of disordered (carbon and carbon–oxygen) clusters, molecules with C7O2H2 stoichiometry in the GDB9-14B dataset, and crystal structures of the form (AlxGayInz)2O3 as proposed in the NOMAD Kaggle competition. Our potential's performance is at least comparable, sometimes significantly more accurate, and often more efficient than other well-known machine-learning potentials for structure prediction. However, primarily, we offer a different perspective on how researchers should consider opportunities in maximizing information storage for features.

In multitask learning (MTL) paradigm, modularity is an effective way to achieve component and parameter reuse as well as system extensibility. In this work, we introduce two enhanced modules named res-fire module (RF) and dimension reduction module(DR) to improve the performance of modular MTL network – PathNet. In addition, in order to further improve the transfer ability of the network, we apply learnable scale parameters to merge the outputs of the modules in the same layer and then scatter to the next layer. Experiments on MNIST, CIFAR, SVHN and MiniImageNet demonstrate that, with the similar scale as PathNet, our architecture achieves remarkable improvement in both transfer ability and expression ability. Our design used x5.23 fewer generations to achieve 99% accuracy on a source-to-target MNIST classification task compared with DeepMind’s PathNet. We also increase the accuracy of CIFARSVHN transfer task by x1.9. Also we get 70.75% accuracy on miniImageNet.

As optimizing neural networks to improve processing speed has become a necessary process in industrial deployment, emerging challenges due to limited storage and computation when adopting neural networks on embedded system need to be addressed. There are some previous studies focusing on training neural networks with low precision weights and activations, like Binarized neural network and DoReFa-Net. Meanwhile, an alternative approach is deployed to reduce number of operations and model size, like MobileNet and SqueezeNet. In this work, by adopting SQ(Scale Quantization) method to quantify activations of each neuron, we have gained a more satisfying result especially in compact network models. For SqueezeDet on KITTI dataset, SQ achieves 22.86% more accuracy on means correct detections, while means location and classification error decrease by 41.84% and 68.57%, compared with DoReFa-Net with 2-bits activations. Additionally, we also propose the SQT(Scale Quantization with Threshold) method to further improve the quantization flexibility. It is worth mentioned that our approach is primarily designed for activations quantization, but it can also be complemented with other orthogonal methods to further achieving efficient neural network processing at the edge.

This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced functions for image quality improvement, including edge-directed image upscaling, guided image filter (GIF) based detail enhancement and noise reduction, multi-view autostereoscopic 3D processing, etc. By leveraging algorithm and architecture co-design, this work efficiently implements these computational intensive display processing functions in a single chip. The chip is fabricated in GF 55nm CMOS technology, and the core size is 38.71mm2 including 1.8M logic gates and 541KB SRAM. The chip works at the maximum operating frequency of 594MHz with the core supply voltage of 1.2V. The maximum input and output video formats reach up to 4K×2K@60fps.

A novel similarity search method, named spiking locality sensitive hash (SLSH), a forward spiking neuron network(SNN) is proposed in this paper. The SLSH architecture is composed of successively connected encoding and fully connected layer. We optimize phase encoding to maximize the difference between corresponding pixels of any two different images. Then we test the performance of the encoding method and the SLSH model on graphic datasets. Experimental results prove that improved phase encoding method based on the difference exhibits the accuracy of 100%, 100% and 92%, which has superiority over previous phase encoding whose accuracies are 93%, 78% and 55% when the noise level is 5%, 20% and 40% respectively. Furthermore, experiments demonstrate that SLSH method is more capable than the traditional Locality-Sensitive Hash(LSH) and the FLY algorithm published in SCIENCE in similarity search. The mean average precision of SLSH is twice of FLY algorithm when the hash length is 5. In addition, the SLSH achieves a good recognition performance even under the influence of noise for MNIST, SVHN and SIFT datasets.

The standard extended Kalman filter-based simultaneously localization and mapping (EKF-SLAM) algorithm has a drawback that it could not handle the sudden motion caused by the motion disturbance. This prevents the SLAM system from real applications. Many techniques have been developed to make the system more robust to the motion disturbance. In this paper, we propose a robust monocular SLAM algorithm. First, when the motion model-based system failed to track the features, a KLT tracker will be activated for each feature. Second, the KLT tracked features are used to update the camera states. Third, the difference between the camera states and the predictions is used to adjust the input motion noise. Finally, we do the standard EKF-SLAM with the new input motion noise. In order to make the system more reliable, a joint compatibility branch and bound algorithm are used to check the outliers, and an IEKF filter is used to make the motion estimation smoother when the camera encounters sudden movement. The experiments are done on an image sequence caught by a shaking hand-held camera, which show that the proposed method is very robust to large motion disturbance.

We present hornet, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued wormhole router network-on-chip (NoC) architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on six separate physical cores on a single die, speedups can exceed a factor of over 5, and when run on a two-die 12-core system with 2-way hyperthreading, speedups exceed 12×. Most hardware parameters are configurable, including memory hierarchy, interconnect geometry, bandwidth, crossbar dimensions, parameters driving power, and thermal effects. A highly parametrized table-based NoC design allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple dimension-ordered routing to complex Valiant, ROMM, O1Turn or PROM schemes, BSOR, and adaptive routing. Hornet can run in network-only mode using synthetic traffic or traces, or directly emulate a MIPS-based multicore. Hornet is freely available under the open-source MIT license at http://csg.csail.mit.edu/hornet/.

Radiation-induced soft error has become an emerging reliability threat to high performance microprocessor design. As the size of on chip cache memory steadily increased for the past decades, resilient techniques against soft errors in cache are becoming increasingly important for processor reliability. However, conventional soft error resilient techniques have significantly increased the access latency and energy consumption in cache memory, thereby resulting in undesirable performance and energy efficiency degradation. The emerging 3D integration technology provides an attractive advantage, as the 3D microarchitecture exhibits heterogeneous soft error resilient characteristics due to the shielding effect of die stacking. Moreover, the 3D shielding effect can offer several inner dies that are inherently invulnerable to soft error, as they are implicitly protected by the outer dies. To exploit the invulnerability benefit, we propose a soft error resilient 3D cache architecture, in which data blocks on the soft error invulnerable dies have no protection against soft error, therefore, access to the data block on the soft error invulnerable die incurs a considerably reduced access latency and energy. Furthermore, we propose to maximize the access on the soft error invulnerable dies by dynamically moving data blocks among different dies, thereby achieving further performance and energy efficiency improvement. Simulation results show that the proposed 3D cache architecture can reduce the power consumption by up to 65% for the L1 instruction cache, 60% for the L1 data cache and 20% for the L2 cache, respectively. In general, the overall IPC performance can be improved by 5% on average.

Most of routing algorithms for On-chip communication are neither application-aware nor routing packets using multiple paths. In addition, they hardly consider link bandwidth variation r esulting from widely applied global asynchronous local synchronous (GALS ) mechanism. In this paper, we propose a bandwidth-based application-aware multipath routing (BAMR) algorithm to assign multiple routing paths by leveraging the knowledge of application and network bandwidth features. With the increase of number of flows resulting from the split of flows, we present a new method named dynamic-amount fixed-number (DAFN) flow control mechanism to avoid deadlock. We compare our algorithm with XY, YX, an d O1TURN with synthetic traffic patterns and traffic trace of parallel implementation of H.264. Experiments demonstrate that BAMR achieves higher throughput with decrease in latency. Furthermore, the proposed algorithm achieves better workload balance by distributing traffic over multiple paths. To address the aforementioned three challenges, we propose a bandwidth-based application-aware mu ltipath routing (BAMR) algorith m. Our algorith m is flexible to different kinds of NoC topologies and traffic patterns. We first decide routing order of flows based on application graph and the bandwidth requirement. Then, considering the transmission capacity of network links, we split some flows into mu ltiple subflows to alleviate network congestion. Our algorithm can detect communication bottlenecks and make split based on link's residual bandwidth. For multipath routing, more flows may increase the possibility of deadlock. To this end, we propose a buffer management mechanism called dynamic- amount fixed-nu mber (DAFN), the number of Virtual Channels (VCs) for each individual router port and VC depth are predetermined at design phase based on the BAMR's results. Specifically, the number of VCs for a specified port at a specified router is depending on the number of flows passing through it. DAFN allocates each VC at a router with an identical global label with assigned flow's label. DAFN achieves deadlock freedom by restricting each flow to its exclusive VC, it takes full advantage of buffer space and avoids deadlock without additional hardware resources. Our work makes following contributions: We propose a mu ltipath routing algorithm named BAM R for GA LS No C. A flow splitting method aiming at to alleviate network congestion is presented, as part of BAMR.A static VC regulator named DAFN, with the co mbination of BAMR to make the full utilization of VC resources and avoid deadlock is also proposed.

There are three main challenges to design an efficient multiview 3DTV SoC:(1)how to organize DRAM address mapping to maximize off-chip bandwidth utilization;(2)how to design a parallel configurable image scaling engine to interpolate various viewpoints in real-time; (3)how to reduce computational complexity of float-point sub-pixel rearrangement with sufficient accuracy. To this end, we present a highly optimized hardware architecture, which saves 38.4% logic and 37.5% memory resources when implementing a multiview 1080P@60Hz 3DTV on the Xilinx XC5VLX330 FPGA.

Fast and accurate machine learning algorithms are needed in many physical applications. However, the learning efficiency is badly subjected to the intensive computation. Knowing that hardware implementation could speed up computation effectively, we use a FPGA hardware platform to implement an on-line kernel learning algorithm, namely the kernel least mean square (KLMS) which adopts the simple survival kernel as the Mercer kernel. By using an on-line quantization method and pipeline technology, the requirement of hardware resources and computation burden can be reduced significantly and the data processing speed can be accelerated apparently without losing accuracy. Finally, a 128-way parallel FPGA platform which works at 200MHz is implemented. It could achieve an average speedup of 6553 versus Matlab running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.

Thanks to its less design complexity, less power consumption and service time, to avoid using virtual channel has became a very attractive approach to building future reliable and massively parallel many-core systems. Furthermore, less area of the light-weight router decrease the probability of failure. To this end, by constructing an acyclic channel dependency graph that breaks all cycles and preserves connectivity of the network, we propose a new deadlock-free fault-tolerant adaptive routing without virtual channel. Extensive experiments of 8x8 2D-mesh network demonstrate 99.73% and 97.56% reliability under uniform random traffic when 10% and 20% of the links are failed.

As the demand for 3DTV keep increasing these years, the conversion from exist 2D videos to 3D ones becomes a new area of research. Depth map generation plays a key point in the process. Two most important clues of depth are geometry of the scene and motion vector. This paper presents an algorithm of depth map generation, which intends to get the depth map combines two aspects of information. Compared to the previous work, our method is improved in finding vanishing point, detect motion vectors, and depth map generation.

We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on 6 separate physical cores on a single die, speedups can exceed a factor of over 5, and when run on a two-die 12-core system with 2-way hyperthreading, speedups exceed 11 ×. Most hardware parameters are configurable, including memory hierarchy, interconnect geometry, bandwidth, crossbar dimensions, and parameters driving power and thermal effects. A highly parametrized table-based NoC design allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple DOR routing to complex Valiant, ROMM, or PROM schemes, BSOR, and adaptive routing. HORNET can run in network-only mode using synthetic traffic or traces, directly emulate a MIPS-based multicore, or function as the memory subsystem for native applications executed under the Pin instrumentation tool. HORNET is freely available under the open-source MIT license at http://csg.csail.mit.edu/hornet/.

This paper proposes a novel video scaler which uses an adaptive polyphase digital filter for image interpolation and possesses a new efficient memory architecture for image data buffering. The proposed adaptive image scaling algorithm is superior to that of bicubic algorithm in preserving details and suppressing ringing artifacts. The new memory architecture, which helps minimize the computational logic and memory usage, significantly simplifies the VLSI design of the scaler. The video scaler can therefore be used independently in any low cost, rational factor image scaling applications without any additional post processing procedures or frame buffering memories.

This paper presents an efficient motion adaptive de-interlacing technique that consists of two main steps, i.e. 4-field extended Gaussian filtering motion detection and adjustable window ELA de-interlacing. Four consecutive interlaced fields are used to detect motion accurately. With a Gaussian filter, the motion detection can eliminate the influence of noise. An adjustable window ELA de-interlacing is adopt to process motion pixels, which can reconstruct image with high quality even in areas with horizontal edge and texture. Experimental results show that the proposed algorithm outperforms previous methods both objectively and subjectively. Based on our method, the high speed VLSI architecture has been designed and implemented. The operating frequency of the chip is 126 MHz that it could process format conversion in real-time for both SDTV and HDTV applications.