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Alternating phase shift technology has been shown to substantially improve focus latitude and resolution for several years. However, the use of phase shift masks to improve the process latitude in gate level lithography has been hindered by the lack of commercially available tools that can convert conventional gate layouts into phase shift mask patterns. A software package has recently become available that allows a user to create phase shift masks to reduce the gate length of features in existing circuit layouts. A digital signal processing chip with 2 million gates has been used as a test vehicle to evaluate the feasibility of phase shifting and processing a large number of devices in a complete circuit. Three wafer lots have been processed with a target feature size of 120 nm with a variation of 25 nm 3σ. The timing circuits of the chips have been tested; those with 120 nm gates showed a nearly fourfold improvement in speed when compared to 240 nm gate circuits at 1 volt operation.

To demonstrate the effectiveness of alternating aperture phase shift lithography and 193nm wavelength lithography for integrated circuit technology, two demonstration devices were designed and processed. In one case, a 2 million transistor integrated circuit was processed with phase shifting and 248nm wavelength lithography. Gate lengths were reduced from 240 to 120nm, resulting in a 100MHz circuit speed at 1.0 volt operation, a threefold improvement. In the second case an 80nm floating gate memory device was fabricated with phase shifting, 193nm wavelength lithography, and anti-reflection control. The lithographic results were confirmed by careful measurements throughout the process sequences and finally by the performance of the devices themselves.

Process integration of two manufacturable high performance 0.5-/spl mu/m CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4. >

A report on a programmable DSP with 32b floating point arithmetic, 32b data path, and an extensive 32b instruction set, implemented in 1.5μ NMOS technology, will be presented. The chip contains 155,000 transistors and operates at 16MHz.

To demonstrate the effectiveness of alternating aperture phase shift lithography for integrated circuit manufacturing, a demonstration device was designed and processed. A 2 million transistor integrated circuit was processed with a phase shifted gate level using 248 nm wavelength lithography. The lithographic results were confirmed by careful feature size measurements throughout the process sequence and finally by the performance of the devices themselves. Gate lengths were reduced from 240 to 120 nm, resulting in fully functional chips with 100 MHz circuit speed at 1.0 V operation, more than a two-fold speed improvement and a record for communication circuits of this type at a low supply voltage.