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In this article, we explore the design of energy-efficient intermittently powered systems (IPSs) using reconfigurable-ferroelectric transistors (R-FEFETs). Utilizing the dynamic tunability between volatile and nonvolatile modes of operation in R-FEFETs, we design nonvolatile flip-flops (NVFFs) and memory (NVM) suitable for IPS. We present two variants of R-FEFET-based NVFFs (RNVFFs): 1) with automatic backup and 2) with need-based backup. While the former offers high backup energy efficiency, the latter offers low normal operation energy. We also present an IPS-specific R-FEFET-based NVM (3T-R) with high energy efficiency compared with FEFET-based 2T NVM. Leveraging these nonvolatile circuits, we map the microcontroller unit (MCU) core registers of an IPS to RNVFFs and its on-chip memory to 3T-R. Subsequently, we analyze system-level implications of improving NVFFs and NVM individually by using R-FEFETs compared with existing FEFET-based designs. Our system-level simulations demonstrate that although we improve the register energy by 55%-67%, the total memory and system-level energy savings obtained from just improving the NVFFs (registers) in the microcontroller core are only 0.60%-5.78% and 0.31%-3.18%, respectively. However, improving the NVM by using 3T-R results in a much larger total memory and system-level energy savings in the range of 37%-40% and 20%-22%, respectively, in the context of a state-of-the-art IPS.

The storage of natural gas in underground reservoirs is an important component of the overall natural gas delivery infrastructure because it permits better management of the supply and demand cycles. Leakage of natural gas to the outside can lead to severe safety and environmental consequences. An integrated Bow-tie (BT) and Bayesian Network (BN) model to assess the probability of gas release is presented in this paper. A barrier-based risk management approach, incorporated in the BT model, provides a useful visualization of the operational hazards and their safe management. The BT approach involves the identification of hazards (or threats) leading to a top event, such as release of natural gas to the external environment. Each hazard has several associated barriers that can either prevent the occurrence of the top event or mitigate the consequences. BT models were constructed for well head and sub-surface systems. However, the BT approach does not consider the interactions between different hazards and barriers. Furthermore, the degradation of the barrier effectiveness over time and space is typically not quantified. BN models were constructed to quantify the failure probabilities of the barriers identified by BT. The BN models compute the probabilities of failure of the wellhead and sub-surface systems. Sensitivity and value of information analyses were conducted using the BN model.

Intermittently Powered Systems (IPS) have an ability to sustain computation progress across multiple power cycles in the presence of unreliable and sporadic harvested energy. However, with the emergence of data-intensive applications to be processed on energy-constrained IPS, it becomes challenging to handle large amounts of data with standard IPS architectures due to the von-Neumann bottleneck. To address this issue, we propose a compute-in-memory (CiM) engine which alleviates the memory-processor bottleneck and enhances energy-efficiency for transient computing workloads in IPS. We present a ferroelectric transistor (FEFET) based memory architecture which supports (a) nonvolatile memory (NVM) storage, (b) standard Boolean and arithmetic operations, (c) cyclic redundancy check for error detection and (d) edge-sensing for wireless sensory networks. Using the proposed CiM engine as a unified NVM, we construct an integrated IPS-CiM architecture based on the TI MSP430 microcontroller system with supply capacitances in the range of 10 nF -1 µF. We evaluate the proposed design with two baselines: hybrid SRAM+NVM and unified NVM architectures, both of which perform standard out-of-memory computing. We observe that for 1µF supply capacitance, IPS-CiM results in energy and performance benefits in the range of 35X-450X and 32X-400X, respectively over conventional microcontroller-based systems.

The rapid proliferation of the Internet-of-Things (IoT) and the dramatic resurgence of artificial intelligence (AI) based application workloads has led to immense interest in performing inference on energy-constrained edge devices. Approximate computing (a design paradigm that yields large energy savings at the cost of a small degradation in application quality) is a promising technique to enable energy-efficient inference at the edge. This paper introduces the concept of an approximate inference system (AxIS) and proposes a systematic methodology to perform joint approximations across different subsystems in a deep neural network-based inference system, leading to significant energy benefits compared to approximating individual subsystems in isolation. We use a smart camera system that executes various convolutional neural network (CNN) based image recognition applications to illustrate how the sensor, memory, compute, and communication subsystems can all be approximated synergistically. We demonstrate our proposed methodology using two variants of a smart camera system: (a) Camedge, where the CNN executes locally on the edge device, and (b) Camcloud, where the edge device sends the captured image to a remote cloud server that executes the CNN. We have prototyped such an approximate inference system using an Altera Stratix IV GX-based Terasic TR4-230 FPGA development board. Experimental results obtained using six CNNs demonstrate significant energy savings (around 1.7× for Camedge and 3.5× for Camcloud) for minimal (

Physically Unclonable Functions (PUFs) have proved to be an effective and low-cost measure against counterfeiting by providing device authentication and secure key storage services. Memory-based PUF implementations are an attractive option due to the ubiquitous nature of memory in electronic devices and the requirement of minimal (or no) additional circuitry. Dynamic Random Access Memory-- (DRAM) based PUFs are particularly advantageous due to their large address space and multiple controllable parameters during response generation. However, prior works on DRAM PUFs use a static response-generation mechanism making them vulnerable to security attacks. Further, they result in slow device authentication, are not applicable to commercial off-the-shelf devices, or require DRAM power cycling prior to authentication. In this article, we propose D-PUF, an intrinsically reconfigurable DRAM PUF based on the idea of DRAM refresh pausing. A key feature of the proposed DRAM PUF is reconfigurability , that is, by varying the DRAM refresh-pause interval, the challenge-response behavior of the PUF can be altered, making it robust to various attacks. The article is broadly divided into two parts. In the first part, we demonstrate the use of D-PUF in performing device authentication through a secure, low-overhead methodology. In the second part, we show the generation of true random numbers using D-PUF. The design is implemented and validated using an Altera Stratix IV GX FPGA-based Terasic TR4-230 development board and several off-the-shelf 1GB DDR3 DRAM modules. Our experimental results demonstrate a 4.3×-6.4× reduction in authentication time compared to prior work. Using controlled temperature and accelerated aging tests, we also demonstrate the robustness of our authentication mechanism to temperature variations and aging effects. Finally, the ability of the design to generate random numbers is verified using the NIST Statistical Test Suite.

Approximate computing has emerged as a popular design paradigm for optimizing the performance and energy consumption of error-resilient applications in domains such as machine learning, graphics, data analytics, etc . Numerous techniques for approximate computing have been proposed at different layers of the system stack, from circuits to architecture to software. In this work, we propose a new technique, called quantized table lookup , for approximating the meta-functions used in the core computational kernels of error-resilient applications. In contrast to prior work that directly approximates the functionality of the meta-functions, the proposed technique instead approximates the input data to the meta-functions by reducing/quantizing them to a much smaller set of values that we call quantized inputs . The small number of quantized inputs enables us to completely replace the energy-intensive arithmetic units in the meta-function with small and energy-efficient lookup tables (called quantized lookup tables or q LUT) that contain precomputed output values corresponding to the quantized inputs. The proposed approximation technique is not only highly generic, but also inherently quality-configurable and input-aware. Quality-configurability and input-awareness are achieved by modulating the size of the q LUT as well as selecting the values of the quantized inputs judiciously based on the statistics of the original input data. To evaluate the proposed technique, we have implemented the dominant meta-functions of nine error-resilient application benchmarks as quantized table lookup based hardware accelerators using 45nm technology. Experimental results demonstrate average energy savings of 46% at the application-level for minimal (

Approximate computing is an emerging design paradigm that leverages the inherent error tolerance present in many applications to improve their power consumption and performance. Due to the forgiving nature of these error-resilient applications, precise input data is not always necessary for them to produce outputs of acceptable quality. This makes the memory subsystem (i.e., the place where data is stored), a suitable component for introducing approximations in return for substantial energy savings. Towards this end, this paper proposes a systematic methodology for constructing a quality configurable approximate DRAM system. Our design is based upon an extensive experimental characterization of memory errors as a function of the DRAM refresh-rate. Leveraging the insights gathered from this characterization, we propose four novel strategies for partitioning the DRAM in a system into a number of quality bins based on the frequency, location, and nature of bit errors in each of the physical pages, while also taking into account the property of variable retention time exhibited by DRAM cells. During data allocation, critical data is placed in the highest quality bin (that contains only accurate pages) and approximate data is allocated to bins sorted in descending order of quality, with the refresh rate serving as the quality control knob. We validate our proposed scheme on several error-resilient applications implemented using an Altera Stratix IV GX FPGA based Terasic TR4-230 development board containing a 1GB DDR3 DRAM module. Experimental results demonstrate a significant improvement in the energy-quality trade-off compared to previous work and show a reduction in DRAM refresh power of up to 73 percent on average with minimal loss in output quality.

Forecasts project that by 2020, there will be around 50 billion devices connected to the Internet of Things (IoT), most of which will operate untethered and unplugged. While environmental energy harvesting is a promising solution to power these IoT edge devices, it introduces new complexities due to the unreliable nature of ambient energy sources. In the presence of an unreliable power supply, frequent checkpointing of the system state becomes imperative, and recent research has proposed the concept of in-situ checkpointing by using ferroelectric RAM (FRAM), an emerging non-volatile memory technology, as unified memory in these systems. Even though an entirely FRAM-based solution provides reliability, it is energy inefficient compared to SRAM due to the higher access latency of FRAM. On the other hand, an entirely SRAM-based solution is highly energy efficient but is unreliable in the face of power loss. This paper advocates an intermediate approach in hybrid FRAM-SRAM microcontrollers that involves judicious memory mapping of program sections to retain the reliability benefits provided by FRAM while performing almost as efficiently as an SRAM-based system. We propose an energy-aware memory mapping technique that maps different program sections to the hybrid FRAM-SRAM microcontroller such that energy consumption is minimized without sacrificing reliability. Our technique consists of eM-map , which performs a one-time characterization to find the optimal memory map for the functions that constitute a program and energy-align , a novel hardware-software technique that aligns the system’s powered-on time intervals to function execution boundaries, which results in further improvements in energy efficiency and performance. Experimental results obtained using the MSP430FR5739 microcontroller demonstrate a significant performance improvement of up to 2x and energy reduction of up to 20% over a state-of-the-art FRAM-based solution. Finally, we present a case study that shows the implementation of our techniques in the context of a real IoT application.

Regulation services (RS) play an important role in maintaining the stability of electric grids by correcting for short-term mismatches between electricity generation and demand. RS providers dynamically supply electricity to the grid or consume electricity from it, in response to regulation signals, in return for economic compensation. This capability is commonly realized through large-scale electrical energy storage (EES) systems based on batteries. However, the highly transient nature of the regulation signals implies that the batteries used for RS are subject to frequent charge and discharge cycles, leading to shortened battery life and thereby impacting the profitability of RS. In this work, we explore the use of hybrid EES (HEES) systems, which combine batteries and supercapacitors, to improve the profitability of RS. HEES systems have the potential to reduce the cost of providing RS by utilizing supercapacitors to respond to the high-frequency components of the regulation signal, prolonging battery life. However, realizing this potential presents several challenges. First, the benefits of HEES systems have a profound dependence on the type of hybrid topology (i.e., active or passive), which results in a tradeoff between the implementation cost and the utilization of the supercapacitor capacity. Second, the allocation of energy storage capacity to batteries and supercapacitors should be carefully determined in the design phase because the reduction in battery replacement cost due to the use of supercapacitors must be balanced against the increased upfront cost for supercapacitors. Third, active HEES systems involve the problem of managing the power flows to batteries and supercapacitors so as to realize maximum cost benefits. To address these challenges, we present a framework for the design and management of a HEES system, so as to maximize the profit from the perspective of an RS provider. This framework consists of i) a design-time capacity optimization phase that determines the best allocation of capacity to batteries and supercapacitors and ii) a run-time management scheme that selects how the different storage devices are orchestrated considering their characteristics and the incoming regulation signal. Our experiments show that, with the proposed capacity optimization and management framework, the use of a passive or an active HEES system can improve the profit of RS providers by 1.16 $\times$ or 5.44 $\times$ , respectively.

In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low-power (sleep) mode when idle and preserving application state either by retaining the data in situ in Static Random Access Memory (SRAM) or by checkpointing it to F lash . However, both of these approaches have notable drawbacks. In situ data retention requires the SRAM to remain powered in sleep mode, while checkpointing to F lash involves significant energy and time overheads. This article proposes a new ultra-low-power sleep mode for microcontrollers that overcomes the limitations of both of these approaches. Our technique, H ypnos , is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10× lower) than the typical operating voltage of the microcontroller. H ypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in sleep mode. We implement and evaluate H ypnos for the TI MSP430G2452 microcontroller and show that the Microcontroller (MCU) draws only 26nA in the proposed sleep mode, which is 4× lower than a baseline sleep mode that preserves SRAM contents. Further, to reduce the overheads associated with performing the voltage scaling, we propose the use of an energy harvesting source for providing the scaled supply voltage and demonstrate (using a light sensing photodiode) that the current consumption in the proposed sleep mode can be reduced to 1nA, which is 100× lower than the current consumption in the baseline low-power mode. We also show that the decrease in sleep-mode power consumption translates to a reduction in application-level energy consumption by as much as 6.45×. By decreasing the average power consumption to such minuscule levels, H ypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

Location is a fundamental service for mobile computing. Typical GPS receivers, although widely available for navigation purposes, may consume too much energy to be useful for many applications. Observing that in many sensing scenarios, the location information can be post-processed when the data is uploaded to a server, we design a cloud-offloaded GPS (CO-GPS) solution that allows a sensing device to aggressively duty-cycle its GPS receiver and log just enough raw GPS signal for post-processing. Leveraging publicly available information such as GNSS satellite ephemeris and an Earth elevation database, a cloud service can derive good quality GPS locations from a few milliseconds of raw data. Using our design of a portable sensing device platform called CLEON, we evaluate the accuracy and efficiency of the solution. Compared to more than 30 seconds of heavy signal processing on standalone GPS receivers, we can achieve three orders of magnitude lower energy consumption per location tagging.

The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms, such as JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant of computing imprecision due to human imperceptibility, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximation statically and are not adaptive to input data. For example, if a fixed approximate hardware configuration is used for an MPEG encoder (i.e., a fixed level of approximation), the output quality varies greatly for different input videos. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes power consumption with the goal of maintaining a particular Peak Signal-to-Noise Ratio (PSNR) threshold for any video. Toward this end, we design reconfigurable adder/subtractor blocks (RABs), which have the ability to modulate their degree of approximation, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. We propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the characteristics of each individual video. Experimental results show that our approach of dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound (PSNR degradation of 1%–10%) across different videos while achieving a power saving up to 38% over a conventional nonapproximated MPEG encoder architecture. Note that although the proposed reconfigurable approximate architecture is presented for the specific case of an MPEG encoder, it can be easily extended to other DSP applications.

With the advent of multiple radio interfaces on a single device, wireless mesh networks start to achieve significant improvement in network capacity, latency, and fault tolerance. The improvement is achieved through concurrent transmissions over different channels utilizing the multiple radio interfaces. However, the introduction of different channels over multiple radios on single mesh node compels to retrospect different issues such as interference, channel diversity, and channel switching from novel perspectives. Due to these novel perspectives, conventional channel assignment techniques proposed for single-radio wireless mesh networks are not generally applicable to the multi-radio cases. Consequently, we have to reconsider the different issues while making a tradeoff among all the available channel assignment options to extract the best performance from a multi-radio wireless mesh network. There are a number of research studies that propose various channel assignment techniques to extract the best performance. In this paper, we present a comprehensive survey on these studies. First, we point out various design issues pertinent to the techniques presented in the studies, and adopt the issues as the basis of our further discussion. Second, we briefly describe several important already-proposed channel assignment techniques. Third, we present a number of channel assignment metrics that are exploited by the already-proposed techniques. Then, depending on the considerations in these techniques, we categorize the techniques and present an exhaustive comparison among them. Nevertheless, we point out a number of real deployments and applications of these techniques in real scenarios. Finally, we identify several open issues for future research with their current status in the literature.

The emergence of the Internet of Things (IoT) and pervasive computing challenges in securely and conveniently connecting devices with limited user interfaces. In particular, discovering and bootstrapping a wireless connection (e.g., Wi-Fi and Bluetooth Low Energy) between two devices that share no prior knowledge, commonly known as pairing, often requires users to go through cumbersome tasks of manually discovering the target device and entering a long passkey. When the devices do not have a proper user interface to enter a passkey, the security of pairing is often given up, leaving the communication vulnerable to a number of attacks. To alleviate this challenge, we propose a usable and secure out-of-band (OOB) communication method called SyncVibe, leveraging the inherent nature of close-proximity transmission of mechanical vibration. SyncVibe utilizes a vibration motor and an accelerometer, that are already ubiquitously available or easy to embed in mobile and wearable devices, to transmit and receive pairing information. By simply keeping two devices in direct contact, the user can bootstrap a secure, high-bandwidth wireless connection without manual pairing procedures. The proposed method maximizes accuracy and effective data throughput with a vibration clock recovery technique, which inserts a minimal amount of extra bit patterns to assure synchronization between the transmitter and the receiver. In addition, SyncVibe can automatically adjust its detection thresholds in response to various vibration noises and transmission media. Our implementation of SyncVibe demonstrates high-accuracy transmission, proving itself as a suitable OOB communication channel for short data transmission for secure device pairing.

In this work, we propose dual mode ferroelectric transistors (D-FEFETs) that exhibit dynamic tuning of operation between volatile and non-volatile modes with the help of a control signal. We utilize the unique features of D-FEFET to design two variants of non-volatile flip-flops (NVFFs). In both designs, D-FEFETs are operated in the volatile mode for normal operations and in the non-volatile mode to backup the state of the flip-flop during a power outage. The first design comprises of a truly embedded non-volatile element (D-FEFET) which enables a fully automatic backup operation. In the second design, we introduce need-based backup, which lowers energy during normal operation at the cost of area with respect to the first design. Compared to a previously proposed FEFET based NVFF, the first design achieves 19% area reduction along with 96% lower backup energy and 9% lower restore energy, but at 14%-35% larger operation energy. The second design shows 11% lower area, 21% lower backup energy, 16% decrease in backup delay and similar operation energy but with a penalty of 17% and 19% in the restore energy and delay, respectively. System-level analysis of the proposed NVFFs in context of a state-of-the-art intermittently-powered system using real benchmarks yielded 5%-33% energy savings.

Transiently Powered Computers (TPCs) are a new class of batteryless embedded systems that depend solely on energy harvested from external sources for performing computations. Enabling long-running computations on TPCs is a major challenge due to the highly intermittent nature of the power supply (often bursts of < 100ms), resulting in frequent system reboots. Prior work seeks to address this issue by frequently checkpointing system state in flash memory, preserving it across power cycles. However, this involves a substantial overhead due to the high erase/write times of flash memory. This article proposes the use of Ferroelectric RAM (FRAM), an emerging nonvolatile memory technology that combines the benefits of SRAM and flash, to seamlessly enable long-running computations in TPCs. We propose a lightweight, in-situ checkpointing technique for TPCs using FRAM that consumes only 30 nJ while decreasing the time taken for saving and restoring a checkpoint to only 21.06μ s , which is over two orders of magnitude lower than the corresponding overhead using flash. We have implemented and evaluated our technique, Q uick R ecall , using the TI MSP430FR5739 FRAM-enabled microcontroller. Experimental results show that our highly-efficient checkpointing translate to significant speedup (1.25x - 8.4x) in program execution time and reduction (∼3x) in application-level energy consumption.

The most-frequently used radio in wireless mesh networks, i.e., 802.11, has short transmission range. Consequently, it mostly imposes multi-hop transmission and thus limits the utilization of radio bandwidth. Emerging radio technologies under the umbrella of 4G, having long transmission range, are capable of enhancing the bandwidth utilization through single-hop transmission at the expense of limiting spatial reuse over the network. Both of these excellences, i.e., the efficient bandwidth utilization and the spatial reuse, are required in case of a concurrent presence of two types of flows--base station oriented and random flows. Therefore, it is necessary to efficiently use both types of radios, i.e., 802.11 and 4G, in next-generation wireless mesh networks, as they are going to experience a mix of the two types of flows. We propose an architecture to guarantee the efficient usage of both the radios through their symbiotic coexistence. Extensive evaluation through analytical modeling, ns-2 simulation, and real testbed experiments reveals that our proposed architecture achieves up to approximately $$6\times $$6× network throughput, 95 % decreased end-to-end delay, and 98 % decreased number of base stations compared to other radio alternatives.

Spike Timing Dependent Plasticity (STDP), wherein synaptic weights are modified based on the temporal correlation between a pair of pre- and post-synaptic (post-neuronal) spikes, is widely used to implement unsupervised learning in Spiking Neural Networks (SNNs). In general, STDP-based learning models disregard the information embedded in post-neuronal spiking frequency. We observe that updating the synaptic weights at the instants of every post-neuronal spike while ignoring the spiking frequency could potentially cause them to learn overlapping representations of multiple input patterns sharing common features. We present STDP-based enhanced plasticity mechanisms that account for the spiking frequency to achieve efficient synaptic learning. First, we utilize low-pass filtered neuronal membrane potential to obtain an estimate of the spiking frequency. We perform STDP-driven weight updates in the event of a post-spike if the filtered potential exceeds a definite threshold. This ensures that plasticity is effected on the dominantly firing neuron that indicates a strong bias in learning the input pattern. Synaptic updates are restrained in the case of sporadic neuronal spiking activity, which implies a weak correlation with the input pattern. This enhances the quality of features encoded by the synapses, resulting in an improvement of 5.8% in the classification accuracy of an SNN of 100 neurons trained for digit recognition. Our simulations further show that the enhanced scheme provides a reduction of 2 χ in the number of weight updates, which leads to improved energy efficiency in event-driven SNN implementations. Second, we explore a neuronal spike-count based enhanced plasticity mechanism. The synapses are modified at the instant of a post-spike if the neuron had fired a certain number of spikes since the preceding update instant. This scheme performs delayed updates at suitable neuronal spiking instants to learn improved synaptic representations. Using this technique, the classification accuracy increased by 4% with 5.2× reduction in the number of weight updates.

Embedded systems play a crucial role in fueling the growth of the Internet-of-Things (IoT) in application domains such as healthcare, home automation, transportation, etc. However, their increasingly network-connected nature, coupled with their ability to access potentially sensitive/confidential information, has given rise to many security and privacy concerns. An additional challenge is the growing number of counterfeit components in these devices, resulting in serious reliability and financial implications. Physically Unclonable Functions (PUFs) are a promising security primitive to help address these concerns. Memory-based PUFs are particularly attractive as they require minimal or no additional hardware for their operation. However, current memory-based PUFs utilize only a single memory technology for constructing the PUF, which has several disadvantages including making them vulnerable to security attacks. In this paper, we propose the design of a new memory-based combination PUF that intelligently combines two memory technologies, SRAM and DRAM, to overcome these shortcomings. The proposed combination PUF exhibits high entropy, supports a large number of challenge-response pairs, and is intrinsically reconfigurable. We have implemented the proposed combination PUF using a Terasic TR4-230 FPGA board and several off-the-shelf SRAMs and DRAMs. Experimental results demonstrate substantial improvements over current memory-based PUFs including the ability to resist various attacks. Extensive authentication tests across a wide temperature range (20 - 60 deg. Celsius) and accelerated aging (12 months) demonstrate the robustness of the proposed design, which achieves a 100% true-positive rate and 0% false-positive rate for authentication across these parameter ranges., Comment: 7 pages, 10 figures

Maintaining the performance of reliable transport protocols, such as transmission control protocol (TCP), over wireless mesh networks (WMNs) is a challenging problem due to the unique characteristics of data transmission over WMNs. The unique characteristics include multi-hop communication over lossy and non-deterministic wireless mediums, data transmission in the absence of a base station, similar traffic patterns over neighboring mesh nodes, etc. One of the reasons for the poor performance of conventional TCP variants over WMNs is that the congestion control mechanisms in conventional TCP variants do not explicitly account for these unique characteristics. To address this problem, this paper proposes a novel artificial intelligence based congestion control technique for reliable data transfer over WMNs. The synergy with artificial intelligence is established by exploiting a carefully designed neural network (NN) in the congestion control mechanism. We analyze the proposed NN based congestion control technique in detail and incorporate it into TCP to create a new variant that we name as intelligent TCP or iTCP. We evaluate the performance of iTCP using both ns-2 simulations and real testbed experiments. Our evaluation results demonstrate that our proposed congestion control technique exhibits a significant improvement in total network throughput and average energy consumption per transmitted bit compared to the congestion control techniques used in other TCP variants.

The early success of wireless sensor networks has led to a new generation of increasingly sophisticated sensor network applications, such as HP's CeNSE. These applications demand high network throughput that easily exceeds the capability of the low-power 802.15.4 radios most commonly used in today's sensor nodes. To address this issue, this paper investigates an energy-efficient approach to supplementing an 802.15.4-based wireless sensor network with high bandwidth, high power, longer range radios, such as 802.11. Exploiting a key observation that the high-bandwidth radio achieves low energy consumption per bit of transmitted data due to its inherent transmission efficiency, we propose a hybrid network architecture that utilizes an optimal density of dual-radio (802.15.4 and 802.11) nodes to augment a sensor network having only 802.15.4 radios. We present a cross-layer mathematical model to calculate this optimal density, which strikes a delicate balance between the low energy consumption per transmitted bit of the high-bandwidth radio and low sleep power of the 802.15.4. Experimental results obtained using a wireless sensor network testbed reveal that our architecture improves the average energy per bit, time elapsed before the first node drains its battery, time elapsed before half of the nodes drain their batteries, and end-to-end delay by significant margins compared with a network having only 802.15.4.

Wireless embedded systems such as sensor nodes and smartphones highlight the importance of reliable data transmission in their advanced applications. Such reliable transmission frequently exhibits a performance below expectation due to inherent resource constraints of the systems. Accurate estimation of round trip time, an important parameter of reliable data transmission, has the potential to significantly improve the performance withstanding the resource constraints. However, contemporary round trip time estimation schemes cannot significantly improve the performance using their stateless estimation schemes as two different states of transmission, success and failure, are equally prominent over wireless mediums. To address this key fact, we propose a novel stateful round trip time estimation scheme for wireless embedded systems, incorporating a light-weight artificial intelligence method. We apply the proposed scheme in a retransmission timeout mechanism of TCP and compare the efficacy of the scheme against that of contemporary estimation schemes. Exhaustive simulation and a testbed experiment reveal that our scheme significantly improves network throughput and average energy per bit compared to other schemes.

Following several recent serious rail accidents in North America, changes in regulation and increased public awareness is driving the need to address gaps in rail safety. The industry and regulators have numerous safety initiatives; however prescriptive standards in combination with a performance based approach could be a powerful tool for understanding and mitigating risk in a cost effective way. This paper reviews the principles of safety risk management that can be applied to safe transportation of flammable hydrocarbons by Rail. FRA’s proposed rulemaking on Risk reduction program and its potential impact on the industry are also addressed. The approach proposed in this paper focuses on existing and new proposed safeguards/barriers and how they could be monitored and managed. The paper aims to set the path forward for structured risk based thinking in managing rail safety. The first part of the paper explains the barrier based risk assessment approach using the Lac Megantic accident as an example. A bow-tie is developed to deconstruct the incident timeline and to capture the safeguards that existed at that time and their working status. This diagram cross references Transport Canada’s Investigation findings. The second part of the paper evaluates the new mitigation measures proposed by FRA HM 251 rulemaking (“Enhanced Tank Car Standards and Operational Controls for High-Hazard Flammable Trains” Final Rulemaking”) as potential safeguards and their impact on the overall risk of transportation. A baseline risk is first established for transporting crude by rail assuming some common safeguards in place. A simple Quantitative Risk Assessment methodology including likelihood and consequence was then used to estimate the base case risk. Risk mitigation and effect of any additional new measures like Changes in Rail Tank Car design, Oil Conditioning, Enhanced Braking to Mitigate Damage in Derailments, Speed Limit changes, Positive train control, Train manning when loading are assessed.

Physically Unclonable Functions (PUFs) have proved to be an effective and low-cost measure against counterfeiting by providing device authentication and secure key storage services. Memory based PUF implementations are an attractive option due to the ubiquitous nature of memory in electronic devices and the requirement of minimal (or no) additional circuitry. DRAM based PUFs are particularly advantageous due to their large address space and multiple controllable parameters during response generation. However, prior works on DRAM PUFs use a static response generation mechanism making them vulnerable to security attacks. Further, they result in very slow device authentication, are not applicable to off-the-shelf DRAM modules, or require DRAM power cycling prior to authentication. In this paper, we propose D-PUF, an intrinsically reconfigurable DRAM PUF based on refresh pausing. A key feature of the proposed DRAM PUF is that it can be reconfigured by varying the refresh-pause interval, which changes it's challenge-response behavior, making it robust against various attacks. We use the PUF to design a secure, low-overhead methodology for performing device authentication. The design is implemented and validated using an Altera Stratix IV GX FPGA based Terasic TR4-230 development board and several off-the-shelf 1GB DDR3 DRAM modules. Our experimental results demonstrate a 4.3×–6.4× reduction in authentication time, compared to previous work. Using controlled temperature and accelerated aging tests, we also demonstrate the robustness of our authentication mechanism to temperature variations and aging effects.

Advances in the physical sciences and engineering enable the development of internet-of-things (IoT) to understand, interface / interact and engineer physical world (systems). However, the deployment of multitude of wireless sensors and agents spanning many application domains (e.g., environmental, healthcare, smart interconnected vehicles and trucks, smart buildings) leads not only to tremendous requirements for communicating massive amounts of multiscale heterogeneous data, but also calls for developing efficient strategies for mathematical modeling of the sensed data while overcoming the energy wall. To address these outstanding challenges, out-of-the-box approaches need to be explored. In this tutorial paper, we discuss these outstanding problems and describe a few far-reaching design methodologies that achieve the most sought after features in autonomous IoT, viz. intelligent mining, smart trustworthy sensing, closed-loop (networked) control, and energy efficiency. Internet-of-things, autonomy, compact yet accurate models, network control, networks-on-chip, manycore.

The lack of post-deployment visibility into system behavior is one of the major challenges in ensuring the reliable operation of implantable medical devices (IMDs). While wireless connectivity is becoming common in IMDs for monitoring device status, conventional wireless links incur significant energy overheads for data acquisition, processing, and active radio transmission. While low-power transceivers have been introduced to reduce the energy consumed by the radio itself, the energy consumed by the microcontroller for processing data and controlling the radio has often been overlooked. As a result, in IMDs that have a stringent energy constraint, prolonged signal monitoring over a wireless channel is infeasible due to this prohibitively high power consumption.To address this challenge, we present TELEPROBE, which enables zero-power probing of signals in IMDs. TELEPROBE is a wireless, oscilloscope-like probing mechanism for IMDs that allows direct readout of analog/digital signals in real-time using an LC tank circuit, without any power overhead imposed on the IMD. We have designed and implemented fully functional prototypes of TeleProbe and demonstrated its utility in the context of two practical usage scenarios: in-situ power analysis and off-chip serial communication bus monitoring in IMDs.

Forecasts project that by 2020, there will be around 50 billion devices connected to the Internet of Things (IoT), most of which will operate untethered and unplugged. While environmental energy harvesting is a promising solution to power these IoT edge devices, it introduces new complexities due to the unreliable nature of ambient energy sources. In the presence of an unreliable power supply, frequent check pointing of system state becomes imperative and recent research proposed the concept of in-situ check pointing by employing ferroelectric RAM (FRAM), an emerging non-volatile memory, as unified memory. Even though an entirely FRAM-based solution provides reliability, it is energy-inefficient compared to SRAM due to a higher access latency. On the other hand, an entirely SRAM-based solution is highly energy efficient, but is unreliable in the face of power loss. This paper advocates an intermediate approach in hybrid FRAM-SRAM MCUs that involves judicious memory mapping of program sections to retain the reliability benefits provided by FRAM while performing almost as efficiently as an SRAM-based system. We propose an energy-aware memory mapping technique that maps different sections to the hybrid FRAM-SRAM MCU such that energy consumption is optimized without sacrificing reliability. Our technique consists of eM-map, which performs a one-time characterization to find the optimal memory map for the functions that constitute a program (this makes our solution portable across platforms) and energy-align, a novel HW/SW technique that aligns the system's powered-on time intervals to function execution boundaries, which results in further improvements in energy efficiency and performance. Our experiments using the MSP430FR5739 microcontroller demonstrate a significant performance improvement of up to 2x and energy reduction of up to 20% over a state-of-the-art FRAM-based solution.

With the growing popularity of wireless sensor networks, network stability has become a key area of current research. Different applications of wireless sensor networks demand stable sensing, coverage, and connectivity throughout their operational periods. In some cases, the death of just a single sensor node might disrupt the stability of the entire network. Therefore, a number of techniques have been proposed to improve the network stability. Clustering is one of the most commonly used techniques in this regard. Most clustering techniques assume the presence of high power sensor nodes called relay nodes and implicitly assume that these relay nodes serve as cluster heads in the network. This assumption may lead to faulty network behavior when any of the relay nodes becomes unavailable to its followers. Moreover, relay node based clustering techniques do not address the heterogeneity of sensor nodes in terms of their residual energies, which frequently occur during the operation of a network. To address these two issues, we present a novel clustering technique, Dynamic Clustering with Relay Nodes (DCRN), by considering the heterogeneity in residual battery capacity and by removing the assumption that relay nodes always serve as cluster-heads. We use an essence of the underlying mechanism of LEACH (Low-Energy Adaptive Clustering Hierarchy), which is one of the most popular clustering solutions for wireless sensor networks. In our work, we present four heuristics to increase network stability periods in terms of the time elapsed before the death of the first node in the network. Based on the proposed heuristics, we devise an algorithm for DCRN and formulate a mathematical model for its long-term rate of energy consumption. Further, we calculate the optimal percentage of relay nodes from our mathematical model. Finally, we verify the efficiency of DCRN and correctness of the mathematical model by exhaustive simulation results. Our simulation results reveal that DCRN enhances the network stability period by a significant margin in comparison to LEACH and its best-known variant.

Micro-scale energy harvesting has emerged as an attractive and increasingly feasible option to alleviate the power supply challenge in a variety of low power applications, such as wireless sensor networks, implantable biomedical devices, etc. While the basic idea and system composition of micro-scale energy harvesting systems have been explored and applied in a number of prototypes in recent years, designing micro-scale efficient energy harvesting systems require an in-depth understanding of various design factors and tradeoffs. This paper provides an overview of the area of micro-scale energy harvesting and addresses various challenges and considerations involved from circuit, architecture and system perspectives. This paper explicitly highlights several subtle but essential design differences that distinguish energy harvesting systems from battery-powered embedded systems. Moreover, we envision the necessity and importance of developing a simulation tool that enables design space exploration and quick performance evaluation at the early design phase. The practical issues, challenges and considerations for implementation of this envisaged simulation tool is discussed in this paper.

Presents information on the 2016 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2016).

Implantable and wearable medical devices are used for monitoring, diagnosis, and treatment of an ever-increasing range of medical conditions, leading to an improved quality of life for patients. The addition of wireless connectivity to medical devices has enabled post-deployment tuning of therapy and access to device data virtually anytime and anywhere but, at the same time, has led to the emergence of security attacks as a critical concern. While cryptography and secure communication protocols may be used to address most known attacks, the lack of a viable secure connection establishment and key exchange mechanism is a fundamental challenge that needs to be addressed. We propose a vibration-based secure side channel between an external device (medical programmer or smartphone) and a medical device. Vibration is an intrinsically short-range, user-perceptible channel that is suitable for realizing physically secure communication at low energy and size/weight overheads. We identify and address key challenges associated with the vibration channel, and propose a vibration-based wakeup and key exchange scheme, named SecureVibe, that is resistant to battery drain attacks. We analyze the risk of acoustic eavesdropping attacks and propose an acoustic masking countermeasure. We demonstrate and evaluate vibration-based wakeup and key exchange between a smartphone and a prototype medical device in the context of a realistic human body model.

Recent years have witnessed a significant rise in the number, duration and variety of video contents, which contribute to the bulk of internet traffic. With increase in smartphone and tablet users, watching videos on mobile devices has become one of its most popular use cases. These devices live on limited battery energy which is still a major bottleneck and a source of user dissatisfaction during video playback. In this paper we introduce an intermediate framework called VIDalizer for power efficient video delivery to smartphones and tablets. This almost transparent to the user, battery aware framework takes away some of the video processing overhead from the device and intelligently tunes its parameters customized for the mobile device while delivering the video using a novel transport protocol. Our preliminary results show that this framework can significantly reduce energy consumption up to 45%-55% of a mobile device without compromising user experience.

Implantable and wearable medical devices (IWMDs) are used for monitoring, diagnosis, and therapy of an ever-increasing range of medical conditions, leading to improved quality of life and outcomes for patients. Advances in the use of IWMDs have been accompanied, and in great part enabled, by increases in their functional complexity, wireless connectivity to allow for postdeployment monitoring, and programmability to allow therapy to be tuned to the evolving needs of each patient. These factors have also led to a rapid growth in concerns about reliability and security of IWMDs, as underscored by recent trends in warnings and recalls of IWMDs due to failures, and a series of successful attacks on IWMDs demonstrated by academic researchers and the hacker community. The unique usage models of IWMDs and the need to provide very high levels of reliability and security under very stringent resource constraints set them apart from other classes of computing platforms. In this chapter, we present the reliability and security challenges faced by designers of IWMDs. We discuss how patient safety and privacy can be compromised by failures of, and security attacks on, the electronic hardware and software within IWMDs. We survey the potential solutions that have been proposed to address these challenges and discuss their merits and limitations.

In recent years, sensor networks have transitioned from being objects of academic research interest to a technology that is frequently being deployed in real-life applications and rapidly being commercialized. However, energy consumption continues to remain a barrier challenge in many sensor network applications that require long lifetimes. Battery-operated sensor nodes have limited energy storage capability due to small form-factors, or operate in environments that rule out frequent energy replenishment, resulting in a mismatch between the available energy budget for system operation and the required energy budget to obtain desired lifetimes. This article surveys several techniques that show promise in addressing and alleviating this energy consumption challenge. In addition to describing recent advances in energy-aware platforms for information processing and communication protocols for sensor collaboration, the article also looks at emerging, hitherto largely unexplored techniques, such as the use of environmental energy harvesting and the optimization of the energy consumed during sensing.

Hazard zones associated with LNG handling activities have been a major point of contention in recent terminal development applications. Debate has reflected primarily worst case scenarios and discussion of these. This paper presents results from a maximum credible event approach. A comparison of results from several models either run by the authors or reported in the literature is presented. While larger scale experimental trials will be necessary to reduce the uncertainty, in the interim a set of base cases are suggested covering both existing trials and credible and worst case events is proposed. This can assist users to assess the degree of conservatism present in quoted modeling approaches and model selections.

Wireless networked embedded systems, such as multimedia terminals, sensor nodes, etc., present a rich domain for making energy/performance/quality tradeoffs based on application needs, network conditions, etc. Energy awareness in these systems is the ability to perform tradeoffs between available battery energy and application quality requirements. In this paper, we show how operating system directed dynamic voltage scaling and dynamic power management can provide for such a capability. We propose a real-time scheduling algorithm that uses runtime feedback about application behavior to provide adaptive power-fidelity tradeoffs. We demonstrate our approach in the context of a static priority-based preemptive task scheduler. Simulation results show that the proposed algorithm results in significant energy savings compared to state-of-the-art dynamic voltage scaling schemes with minimal loss in system fidelity. We have implemented our scheduling algorithm into the eCos real-time operating system running on an Intel XScale-based variable voltage platform. Experimental results obtained using this platform confirm the effectiveness of our technique

As embedded systems are being networked, often wirelessly, an increasingly larger share of their total energy budget is due to the communication. This necessitates the development of power management techniques that address communication subsystems, such as radios, as opposed to computation subsystems, such as embedded processors, to which most of the research effort thus far has been devoted. In this paper, we present techniques for energy efficient packet scheduling and fair queuing in wireless communication systems. Our techniques are based on an extensive slack management approach that dynamically adapts the output rate of the system in accordance with the input packet arrival rate. We use a recently proposed radio power management technique, dynamic modulation scaling (DMS), as a control knob to enable energy-latency trade-offs during wireless packet transmission. We first analyze a single input stream scenario, and describe a rate adaptation technique that results in significantly lower energy consumption (reductions of up to 10 ×), while still bounding the resulting packet delays. By appropriately setting the various parameters of our algorithm, the system can be made to traverse the energy-latency-fidelity trade-off space. We extend our techniques to a multiple input stream scenario, and present E 2 WFQ , an energy efficient version of the weighted fair queuing (WFQ) algorithm for fair packet scheduling. Simulation results show that large energy savings can be obtained through the use of E 2 WFQ , with only a small, bounded increase in worst case packet latency. Further, our results demonstrate that E 2 WFQ does not adversely affect the throughput allocation (and hence, fairness) of WFQ.

System-level power management has become a key technique to render modern wireless communication devices economically viable. Despite their relatively large impact on the system energy consumption, power management for radios has been limited to shutdown-based schemes, while processors have benefited from superior techniques based on dynamic voltage scaling (DVS). However, similar scaling approaches that trade-off energy versus performance are also available for radios. To utilize these in radio power management, existing packet scheduling policies have to be thoroughly rethought to make them energy-aware, essentially opening a whole new set of challenges the same way the introduction of DVS did to CPU task scheduling. We use one specific scaling technique, dynamic modulation scaling (DMS), as a vehicle to outline these challenges, and to introduce the intricacies caused by the nonpreemptive nature of packet scheduling and the time-varying wireless channel.

This article describes architectural and algorithmic approaches that designers can use to enhance the energy awareness of wireless sensor networks. The article starts off with an analysis of the power consumption characteristics of typical sensor node architectures and identifies the various factors that affect system lifetime. We then present a suite of techniques that perform aggressive energy optimization while targeting all stages of sensor network design, from individual nodes to the entire network. Maximizing network lifetime requires the use of a well-structured design methodology, which enables energy-aware design and operation of all aspects of the sensor network, from the underlying hardware platform to the application software and network protocols. Adopting such a holistic approach ensures that energy awareness is incorporated not only into individual sensor nodes but also into groups of communicating nodes and the entire sensor network. By following an energy-aware design methodology based on techniques such as in this article, designers can enhance network lifetime by orders of magnitude.

Ambient energy harvesting is a well-known technique in wireless sensing systems. To minimize energy consumption, such systems are typically designed to be heavily duty-cycled with long idle times and are characteristically lightweight in computation. Often, these systems contain a dedicated energy harvesting transducer that is independent of the sensing sub-system. As a result, any output energy from the sensor ends up being unused (and hence, lost) when the system is in idle state. This work proposes a novel system architecture and corresponding hardware platform, Senergy, in which the energy harvested from a sensor during idle time is utilized to power the system. Senergy is based on an ultra-low power charge pump circuit that boosts input voltages as low as 330mV. We successfully demonstrate our proposed architecture with an RF-capable (2.4GHz ISM band) sensing platform utilizing a photovoltaic sensor as the sole energy source. We evaluate our approach on two applications, namely adaptive transmission of sensor data and providing an uninterrupted power supply to an on-board real time clock.

Regulation services (RS) play an important role in maintaining the stability of electric grids by correcting for short-term mismatches between electricity generation and demand. RS providers dynamically supply electricity to the grid or consume electricity from it, in response to regulation signals, in return for economic compensation. This capability is commonly realized through large-scale electrical energy storage (EES) systems based on batteries. However, the highly transient nature of the regulation signals implies that the batteries used for RS are subject to frequent charge and discharge cycles, leading to shortened battery life and thereby impacting the profitability of RS. In this work, we explore the use of hybrid EES (HEES) systems, which combine batteries and supercapacitors, to improve the profitability of RS. HEES systems have the potential to reduce the cost of providing RS by utilizing supercapacitors to respond to the high-frequency components of the regulation signal, prolonging battery life. However, realizing this potential presents several challenges. First, the benefits of HEES systems are profoundly impacted by the allocation of capacity to batteries and supercapacitors. This is because the reduction in battery replacement cost due to the use of supercapacitors must be traded off against the increased upfront cost for supercapacitors. Second, HEES systems introduce the problem of how to manage the power flows to the batteries and supercapacitors so as to realize maximum benefits. To address these challenges, we present a framework for the design and management of a HEES system, so as to maximize profit from the perspective of an RS provider. At design time, we propose a capacity optimization framework that determines the best allocation of capacity to batteries and supercapacitors. During system operation, the proposed management scheme selects how the different storage devices are orchestrated considering their characteristics, as well as the incoming regulation signal. Our experiments suggest that, with the proposed capacity optimization and management framework, the use of HEES systems can improve the profit of RS providers by 79%–196%.

In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low power (sleep) state when idle, and preserving application state either by retaining the data in-situ in SRAM, or by checkpointing it to Flash. However, both these approaches have notable drawbacks. In-situ data retention requires the SRAM to remain powered in sleep mode, while checkpointing to Flash involves significant energy and time overheads. This paper proposes a new ultra-low power sleep mode for microcontrollers that overcomes the limitations of both these approaches. Our technique, Hypnos, is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10x lower) than the typical operating voltage of the microcontroller. Hypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in sleep mode. We implement and evaluate Hypnos for the TI MSP430G2452 microcontroller and show that the MCU draws only 26nA in the proposed sleep mode, which is 4x lower than any existing sleep mode that preserves SRAM contents. Further, we show that a complete wireless sensing system using Hypnos only depletes battery capacity by 42.6nAh in an hour. By decreasing the average power consumption to such minuscule levels, Hypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

Monitoring of bladder pressure, known as cystometry, is a key diagnostic tool in urodynamic studies of patients that exhibit lower urinary tract symptoms. Over the past few years, there has been an increased interest in ambulatory urodynamics due to the increased convenience and more realistic monitoring environment. This paper presents an ultra-low power implantable wireless platform, UP-Link, for long-term ambulatory bladder pressure monitoring. The proposed platform, which is built using off-the-shelf components and uses the MICS (Medical Implant Communication Service) radio frequency band for communication, enables more cost-effective and rapid development compared to existing ASIC-based solutions. The UP-Link platform is powered by two coin cell batteries with a total capacity of 560mAh and has an estimated battery life of several months to years. Results obtained through in vitro experiments demonstrate that the pressure data measured using UP-Link shows excellent agreement (0.995 using the intraclass correlation coefficient method) with measurements obtained using a commercial pressure gauge. An accelerated battery-life test was also performed, the results of which validate our lifetime estimates. The longevity of the UPLink platform enables ambulatory urodynamic studies at much longer time scales than current practice.

Various industry forecasts project that, by 2020, there will be around 50 billion devices connected to the Internet of Things (IoT), helping to engineer new solutions to societal-scale problems such as healthcare, energy conservation, transportation, etc. Most of these devices will be wireless due to the expense, inconvenience, or in some cases, the sheer infeasibility of wiring them. Further, many of them will have stringent size constraints. With no cord for power and limited space for a battery, powering these devices (to achieve several months to possibly years of unattended operation) becomes a daunting challenge. This paper highlights some promising directions for addressing this challenge, focusing on three main building blocks: (a) the design of ultra-low power hardware platforms that integrate computing, sensing, storage, and wireless connectivity in a tiny form factor, (b) the development of intelligent system-level power management techniques, and (c) the use of environmental energy harvesting to make IoT devices self-powered, thus decreasing -- in some cases, even eliminating -- their dependence on batteries. We discuss these building blocks in detail and illustrate case-studies of systems that use them judiciously, including the QUBE wireless embedded platform, which exploits the characteristics of emerging non-volatile memory technologies to seamlessly and efficiently enable long-running computations in systems that experience frequent power loss (i.e., intermittently powered systems).

Diversified applications of wireless sensor networks demand reliable data transmission, which generally experiences limited performance owing to the inherent resource constraints of sensor nodes. Estimated round trip time is one of the prominent aspects of reliable transmissions that possesses a potential to enhance the performance sustaining the resource constraints. Therefore, we have already proposed an efficient technique for estimating round trip time over wireless sensor networks. We have evaluated the proposed technique over low-data-rate networks, consisting low-bandwidth radios, considering classical deployments of sensor networks. However, recent deployments of wireless sensor networks have started to exploit high-bandwidth radios as they are now experiencing high-data-rate transmission. Therefore, in this paper, we evaluate the proposed estimation technique over high-data-rate wireless sensor networks consisting high-bandwidth radios. Our evaluation through both real testbed experiments and ns-2 simulation reveals significant performance improvement using the proposed technique compared to that using other existing techniques.

Transiently Powered Computers (TPCs) are a new class of batteryless embedded systems that depend solely on energy harvested from external sources for performing computations. Enabling long-running computations on TPCs is a major challenge due to the highly intermittent nature of the power supply (often bursts of

The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms such as JPEG, MPEG, etc., are particularly attractive candidates for approximate computing since they are tolerant of computing imprecision due to human imperceptibility, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximation statically and are not adaptive to input data. For example, if a fixed approximate hardware configuration is used for an MPEG encoder (i.e., a fixed level of approximation), the output quality varies greatly for different input videos. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes power consumption while maintaining a particular PSNR threshold for any video. Experimental results show that our approach of dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound (PSNR degradation of 5-20%) across different videos while achieving a power savings of 13-18% over a conventional non-approximated MPEG encoder architecture. Although the proposed reconfigurable approximate architecture is presented for the specific case of an MPEG encoder, it can be easily extended to other DSP applications.

Components used as building blocks (e.g., functional units) in conventional HLS techniques are assumed to have fixed latency values. Variable-latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on the input values. While variable-latency units offer potential for performance improvement, we demonstrate that realization of this potential requires that HLS be adapted suitably (sub-optimal use of variable-latency units can lead to performance degradation, or unnecessarily high area overheads). Our techniques to incorporate variable-latency units into HLS ensure that the performance improvement is maximized, while minimizing area overheads or satisfying resource constraints. These techniques are not restricted to specific HLS tools/algorithms, and can be plugged in to any generic HLS system. Since area overheads may still be incurred due to the use of variable-latency units, we present a novel technique, based on the concept of reduced variable-latency units, to further reduce area overheads. Reduced variable-latency units only implement the low-latency case behavior of complete variable-latency units. We demonstrate that the use of reduced variable-latency units significantly reduces area overheads, and sometimes results in improvements in performance while simultaneously reducing the area of the register transfer level implementation. Experimental results show that the proposed variable-latency-unit-based synthesis techniques achieve a performance improvement of up to 1.6/spl times/ (average of 1.4/spl times/) over a state-of-the-art HLS tool, with minimal area overheads (average of 5.3%). The use of reduced variable-latency units leads to a performance improvement of up to 1.6/spl times/ (average of 1.3/spl times/), with a simultaneous area reduction of up to 17.9% (10.6% on the average).

Recent advances in superlattice based thermoelectric (TE) materials hold promise for realizing thin-film TE modules that can be embedded inside a chip package. Significant research effort has been devoted towards evaluating the feasibility of embedded thin-film TE modules for hot-spot cooling applications. Note, these embedded TE modules can also harvest electrical energy from the waste heat dissipated by the chip. In this work, we explore the on-chip energy harvesting capabilities of Bi2Te3/Sb2Te3 superlattice based TE materials using rigorous finite element simulations. In addition, an inductive DC-DC power converter was designed for up-converting the output voltage of the TE module. The end-to-end conversion efficiency of this harvesting system has been optimized through the co-design of TE module and its power converter. Using the optimized harvesting system, we show that it is possible to harvest up to 4mW from a 3mm2 hot-spot with a heat-flux of 200W/cm2. Our results indicate that designing the TE module and its power converter independently could lead to a sub-optimal system. In addition, the contact parasitics in the TE module degrade the intrinsic performance of the TE material by as much as 3x. However, when the contact parasitics in the TE module are reduced, the system can suffer from increased resistance mismatches as well as conduction power losses in the converter circuit. Therefore, even if contact parasitics are reduced, it may not provide a significant improvement in the energy harvesting performance at the system level.