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The ability to estimate the uncertainty of predictions made by a neural network is essential when applying neural networks to tasks such as medical diagnosis and autonomous vehicles. The approach is of particular relevance when deploying the networks on devices with limited hardware resources, but existing competency-aware neural networks largely ignore any resource constraints. Here we examine the relationship between hardware platforms and the competency awareness of a neural network. We highlight the impact of two key areas of hardware development — increasing memory size of accelerator architectures and device-to-device variation in the emerging devices typically used in in-memory computing — on uncertainty estimation quality. We also consider the challenges that developments in uncertainty estimation methods impose on hardware designs. Finally, we explore the innovations required in terms of hardware, software, and hardware–software co-design in order to build future competency-aware neural networks. This Perspective examines the relationship between hardware platforms and the competency awareness of a neural network, highlighting how hardware developments can impact uncertainty estimation quality, and exploring the innovations required in order to build competency-aware neural networks in resource constrained hardware platforms.

The index is a fundamental component in data intensive systems to accelerate data retrieval operations. In the design of Non-Volatile Memory (NVM) based indexes, the hash-based structure is one of the most promising candidates since it can take full advantages of byte-addressable property of NVM to perform query operations with constant time complexity. However, we found that the basic operation, “rehash operation”, may incur a large number of write activities on NVM, which is harmful to the endurance of NVM, and will cause drastic performance degradation. Additionally, range query operations cannot be efficiently conducted on hash-based indexes. In this paper, we first investigate how to design an NVM-friendly hash-based structure with the considerations of endurance and performance issues. Then, we propose a novel indexing scheme called “Bucket Hash”, which can significantly reduce the overhead caused by rehash operations and range query operations. We evaluate the proposed Bucket Hash using YCSB workloads. Compared with existing indexes, Bucket Hash achieves 40% reduction on average in the number of NVM writes, meanwhile gaining 30% improvement on timing performance.

Recently, it is reported that the-state-of-the-art secure protocol is able to segment a three-dimensional heart CT scan in roughly 3,000 seconds, without revealing any sensitive information related to the parties involved in the computation. In this work, building upon the existing mix-protocol approach, we make use of the trusted execution environment (TEE) to implement a more efficient privacy-preserving medical image segmentation protocol. In the experiment, we show that by offloading the computations of single-party operators to trusted hardware, the latency for a round of privacy-preserving segmentation can be further reduced by 25×.

Transformer-based deep learning models have increasingly demonstrated high accuracy on many natural language processing (NLP) tasks. In this paper, we propose a compression-compilation co-design framework that can guarantee the identified model to meet both resource and real-time specifications of mobile devices. Our framework applies a compiler-aware neural architecture optimization method (CANAO), which can generate the optimal compressed model that balances both accuracy and latency. We are able to achieve up to 7.8x speedup compared with TensorFlow-Lite with only minor accuracy loss. We present two types of BERT applications on mobile devices: Question Answering (QA) and Text Generation. Both can be executed in real-time with latency as low as 45ms. Videos for demonstrating the framework can be found on https://www.youtube.com/watch?v=_WIRvK_2PZI, arXiv admin note: substantial text overlap with arXiv:2009.06823

In many recent novel blockchain consensuses, deep learning training procedure becomes the task for miners to prove their workload, thus the computation power of miners will not purely be spent on the hash puzzle. Therefore, the hardware and energy will support the blockchain service and deep learning training at the same time. The incentive of miners is to earn tokens and individual miners will find mining pools become more competitive. To the best of our knowledgeWe are the first to demonstrate a mining pool solution for novel consensuses based on deep learning. This work adopts from exist Proof-of-Deep-Learning (PoDL) as the consensus and Neural Architecture Search (NAS) as the workload. The mining pool manager partitions the full searching space into subspaces and all miners contributes to the NAS task in the assigned tasks. The strong miners are assigned for exploration and the weak miners are assigned for exploitation. In section IV, it shows the performance of this mining pool is more competitive than an individual miner in conducting NAS as workload.

Real-time Deep Neural Network (DNN) inference with low-latency requirement has become increasingly important for numerous applications in both cloud computing (e.g., Apple's Siri) and edge computing (e.g., Google/Waymo's driverless car). FPGA-based DNN accelerators have demonstrated both superior flexibility and performance; in addition, for real-time inference with low batch size, FPGA is expected to achieve further performance improvement. However, the performance gain from the single-FPGA design is obstructed by the limited on-chip resource. In this paper, we employ multiple FPGAs to cooperatively run DNNs with the objective of achieving super-linear speed-up against single-FPGA design. In implementing such systems, we found two barriers that hinder us from achieving the design goal: (1) the lack of a clear partition scheme for each DNN layer to fully exploit parallelism, and (2) the insufficient bandwidth between the off-chip memory and the accelerator due to the growing size of DNNs. To tackle these issues, we propose a general framework, "Super-LIP", which can support different kinds of DNNs. In this paper, we take Convolutional Neural Network (CNN) as a vehicle to illustrate Super-LIP. We first formulate an accurate system-level model to support the exploration of best partition schemes. Then, we develop a novel design methodology to effectively alleviate the heavy loads on memory bandwidth by moving traffic from memory bus to inter-FPGA links. We implement Super-LIP based on ZCU102 FPGA boards. Results demonstrate that Super-LIP with 2 FPGAs can achieve 3.48x speedup, compared to the state-of-the-art single-FPGA design. What is more, as the number of FPGAs scales up, the system latency can be further reduced while maintaining high energy efficiency., Accepted by ESWEEK CODES+ISSS 2019, nominated as best paper. Appear in ACM TECS

Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent cores, while communication efficiency among these cores will be oppositely affected over conventional network-on-chip (NoC). Recently, SMART NoC architecture is proposed, enabling single-cycle multi-hop bypass channels to be built between distant cores at runtime, to reduce communication latency. However, communication efficiency of SMART NoC will be diminished by communication contention, which will in turn decrease system performance. In this paper, we first propose an Integer-Linear Programming (ILP) model to properly address communication problem, which generates the optimal solutions with the consideration of inter-processor communication. We further present a novel heuristic algorithm for task mapping in dark silicon many-core systems, called TopoMap, on top of SMART architecture, which can effectively solve communication contention problem in polynomial time. With fine-grained consideration of chip thermal reliability and inter-processor communication, presented approaches are able to control the reconfigurability of NoC communication topology in task mapping and scheduling. Thermal-safe system is guaranteed by physically decentralized active cores, and communication overhead is reduced by the minimized communication contention and maximized bypass routing. Performance evaluation on PARSEC shows the applicability and effectiveness of the proposed techniques, which achieve on average 42.5 and 32.4 percent improvement in communication and application performance, and 32.3 percent reduction in system energy consumption, compared with state-of-the-art techniques. TopoMap only introduces 1.8 percent performance difference compared to ILP model and is more scalable to large-size NoCs. Accepted version

A pruning-based AutoML framework for run-time reconfigurability, namely RT3, is proposed in this work. This enables Transformer-based large Natural Language Processing (NLP) models to be efficiently executed on resource-constrained mobile devices and reconfigured (i.e., switching models for dynamic hardware conditions) at run-time. Such reconfigurability is the key to save energy for battery-powered mobile devices, which widely use dynamic voltage and frequency scaling (DVFS) technique for hardware reconfiguration to prolong battery life. In this work, we creatively explore a hybrid block-structured pruning (BP) and pattern pruning (PP) for Transformer-based models and first attempt to combine hardware and software reconfiguration to maximally save energy for battery-powered mobile devices. Specifically, RT3 integrates two-level optimizations: First, it utilizes an efficient BP as the first-step compression for resource-constrained mobile devices; then, RT3 heuristically generates a shrunken search space based on the first level optimization and searches multiple pattern sets with diverse sparsity for PP via reinforcement learning to support lightweight software reconfiguration, which corresponds to available frequency levels of DVFS (i.e., hardware reconfiguration). At run-time, RT3 can switch the lightweight pattern sets within 45ms to guarantee the required real-time constraint at different frequency levels. Results further show that RT3 can prolong battery life over 4x improvement with less than 1% accuracy loss for Transformer and 1.5% score decrease for DistilBERT., 7 pages, 5 figures

Along with the development of AI democratization, the machine learning approach, in particular neural networks, has been applied to wide-range applications. In different application scenarios, the neural network will be accelerated on the tailored computing platform. The acceleration of neural networks on classical computing platforms, such as CPU, GPU, FPGA, ASIC, has been widely studied; however, when the scale of the application consistently grows up, the memory bottleneck becomes obvious, widely known as memory-wall. In response to such a challenge, advanced quantum computing, which can represent 2^N states with N quantum bits (qubits), is regarded as a promising solution. It is imminent to know how to design the quantum circuit for accelerating neural networks. Most recently, there are initial works studying how to map neural networks to actual quantum processors. To better understand the state-of-the-art design and inspire new design methodology, this paper carries out a case study to demonstrate an end-to-end implementation. On the neural network side, we employ the multilayer perceptron to complete image classification tasks using the standard and widely used MNIST dataset. On the quantum computing side, we target IBM Quantum processors, which can be programmed and simulated by using IBM Qiskit. This work targets the acceleration of the inference phase of a trained neural network on the quantum processor. Along with the case study, we will demonstrate the typical procedure for mapping neural networks to quantum circuits., Comment: Invited paper at ASP-DAC'21

Real-time cardiac magnetic resonance imaging (MRI) plays an increasingly important role in guiding various cardiac interventions. In order to provide better visual assistance, the cine MRI frames need to be segmented on-the-fly to avoid noticeable visual lag. In addition, considering reliability and patient data privacy, the computation is preferably done on local hardware. State-of-the-art MRI segmentation methods mostly focus on accuracy only, and can hardly be adopted for real-time application or on local hardware. In this work, we present the first hardware-aware multi-scale neural architecture search (NAS) framework for real-time 3D cardiac cine MRI segmentation. The proposed framework incorporates a latency regularization term into the loss function to handle real-time constraints, with the consideration of underlying hardware. In addition, the formulation is fully differentiable with respect to the architecture parameters, so that stochastic gradient descent (SGD) can be used for optimization to reduce the computation cost while maintaining optimization quality. Experimental results on ACDC MICCAI 2017 dataset demonstrate that our hardware-aware multi-scale NAS framework can reduce the latency by up to 3.5 times and satisfy the real-time constraints, while still achieving competitive segmentation accuracy, compared with the state-of-the-art NAS segmentation framework., Comment: 8 pages, conference

Recently, Long Short-Term Memory (LSTM), a type of recurrent neural network, has been widely employed in realtime applications, such as speech recognition, word segmentation, machine translation, etc. While existing works demonstrate that LSTM can be efficiently deployed in cloud platforms, the high communication latency between cloud and edge will drastically reduce its efficiency. Therefore, efficient LSTM accelerators at the edge are highly demanded. The limited resource in edge devices and the heterogeneous operations in LSTM (e.g., LSTM gates) bring challenges for the LSTM accelerator design. It seems straightforward to implement each operation as a specific hardware kernel. However, the data dependency among gates leads to significant running stalls in the existing heterogeneous-kernel accelerator, resulting in low parallelism and low resource utilization. To overcome the above challenges, this work proposes a novel generic LSTM accelerator design for Field-programmable Gate Array (FPGA) and Application-specific Integrated Circuit (ASIC) platforms, where two fundamental computing patterns (i.e., element-wise multiplication and addition) are incorporated in a unified computing kernel to execute operations in all LSTM gates simultaneously. Thus, the running stalls caused by heterogeneous kernels can be eliminated, achieving full parallelism in LSTM. The proposed technique and architecture are validated on Xilinx PYNQ-Z1 FPGA which can fully utilize the available resource, achieving 10x faster in inference time and 15.2x improvement in computing power efficiency compared with the state-of-the-art LSTM accelerator.

Despite the pursuit of quantum supremacy in various applications, the power of quantum computers in machine learning (such as neural network models) has mostly remained unknown, primarily due to a missing link that effectively designs a neural network model suitable for quantum circuit implementation. In this article, we present the first co-design framework, namelyQuantumFlow, to fixed the missing link. QuantumFlow consists of a novel quantum-friendly neural network (QF-Net) design, an automatic tool (QF-Map) to generate the quantum circuit (QF-Circ) for QF-Net, and a theoretic-based execution engine (QF-FB) to efficiently support the training of QF-Net on a classical computer. We discover that, in order to make full use of the strength of quantum representation, data in QF-Net is best modeled as random variables rather than real numbers. Moreover, instead of using the classical batch normalization (which is key to achieve high accuracy for deep neural networks), a quantum-aware batch normalization method is proposed for QF-Net. Evaluation results show that QF-Net can achieve 97.01% accuracy in distinguishing digits 3 and 6 in the widely used MNIST dataset, which is 14.55% higher than the state-of-the-art quantum-aware implementation. A case study on a binary classification application is conducted. Running on IBM Quantum processor’s“ibmq_essex” backend, a neural network designed by QuantumFlow can achieve 82% accuracy. To the best of our knowledge,QuantumFlow is the first framework that co-designs both the machine learning model and its quantum circuit.

Hardware-aware Neural Architecture Search (NAS), which automatically finds an architecture that works best on a given hardware design, has prevailed in response to the ever-growing demand for real-time Artificial Intelligence (AI). However, in many situations, the underlying hardware is not pre-determined. We argue that simply assuming an arbitrary yet fixed hardware design will lead to inferior solutions, and it is best to co-explore neural architecture space and hardware design space for the best pair of neural architecture and hardware design. To demonstrate this, we employ Network-on-Chip (NoC) as the infrastructure and propose a novel framework, namely NANDS, to co-explore NAS space and NoC Design Search (NDS) space with the objective to maximize accuracy and throughput. Since two metrics are tightly coupled, we develop a multi-phase manager to guide NANDS to gradually converge to solutions with the best accuracy-throughput tradeoff. On top of it, we propose techniques to detect and alleviate timing performance bottleneck, which allows better and more efficient exploration of NDS space. Experimental results on common datasets, CIFAR10, CIFAR-100 and STL-10, show that compared with state-of-the-art hardware-aware NAS, NANDS can achieve 42.99% higher throughput along with 1.58% accuracy improvement. There are cases where hardware-aware NAS cannot find any feasible solutions while NANDS can.

The strict security requirements placed on medical records by various privacy regulations become major obstacles in the age of big data. To ensure efficient machine learning as a service schemes while protecting data confidentiality, in this work, we propose blind UNET (BUNET), a secure protocol that implements privacy-preserving medical image segmentation based on the UNET architecture. In BUNET, we efficiently utilize cryptographic primitives such as homomorphic encryption and garbled circuits (GC) to design a complete secure protocol for the UNET neural architecture. In addition, we perform extensive architectural search in reducing the computational bottleneck of GC-based secure activation protocols with high-dimensional input data. In the experiment, we thoroughly examine the parameter space of our protocol, and show that we can achieve up to 14x inference time reduction compared to the-state-of-the-art secure inference technique on a baseline architecture with negligible accuracy degradation.

Dark silicon refers to the phenomenon that a fraction of a many-core chip has to become “dark” or “dim” in order to guarantee the system to be kept in a safe temperature range and allowable power budget. Techniques have been developed to selectively activate non-adjacent cores on many-core chip to avoid temperature hotspot, while resulting unexpected increase of communication overhead due to the longer average distance between active cores, and in turn affecting application performance and energy efficiency, when Network-on-Chip (NoC) is used as a scalable communication subsystem. To address the brand-new challenges brought by dark silicon, in this paper, we present FoToNoC , a Fo lded To rus-like NoC , coupled with a hierarchical management strategy for heterogeneous many-core systems. On top of it, objectives of maximizing application performance, energy efficiency and chip reliability are isolated and well achieved by hardware-software co-design in several different phases, including application mapping and scheduling, cluster management and DVFS control. Evaluations on PARSEC benchmark applications demonstrate the significance of the entire strategy. Compared with state-of-the-art approaches, the proposed FoToNoC organization can achieve on average 35.4 and 35.2 percent on communication efficiency and application performance improvement, respectively, when maintaining the safe chip temperature. The hierarchical cluster-based management strategy can further reduce an average 34.6 percent of the total energy consumption with a notable reduction on the chip peak temperature. The significant achievements on system energy efficiency and the reduction on chip temperature of H.264 decoder and DSP-stone benchmarks additionally verify the effectiveness of the proposed methods.

Strategic and tactical planning is integrally considered in agile manufacturing scenarios.Solutions of the optimal assignment problem for large-scale supply chains are presented.Mixed integer linear programming method is presented to model the assignment problem.Efficient dynamic programming algorithm is devised to obtain the optimal assignment. While the production process evolves toward modularization and decentralization, the design of supply chain networks, in particular considering the agile manufacturing scenario, becomes challenging due to the following reasons: (1) supply chains that produce a network of components become large-scale; (2) the number of possible assignments is growing exponentially as the increasing choices of plants for components. In this paper, the assignment problem considers the strategic and tactical decisions together, which involves the mapping of components to geographically distributed plants, the selection of logistics services between the mapped plants, and the allocation of inventories in each plant. The goal of this paper is to find the optimal assignment with the minimum total cost under the constraint of production rate. We first mathematically formulate the problem as a mixed integer linear program. Then, by deriving the properties of pipelined production in supply chain networks, we develop dynamic programming algorithms to efficiently obtain the optimal assignments. By the consideration of high degree of pipelining, our techniques can make a good tradeoff between high production rate and low operation cost. Extensive computational experiments show that the proposed algorithms can find high quality solutions, which achieve significant improvement compared with the initiative approaches.

In dark silicon many-core systems, system-level techniques have been developed to selectively activate nonadjacent cores in physical locations to maintain the allowable power budget and eliminate thermal hotspot. However, this will unexpectedly increase communication overhead due to the longer average distance between active cores in a typical mesh-based Network-on-Chip (NoC), and in turn reduce application performance. Inspired by ARM’s big.LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) which enables energy-efficient solutions, in this paper, we propose two alternative hardware–software collaborated techniques to address the temperature/communication conflict in the dark silicon era. A Folded Torus-like NoC, FoToNoC, is presented to address the Cluster-switching based heterogeneous system, and a Quad-core-group based NoC, QcNoC, is presented to address the In-kernel switcher based heterogeneous system. Matched management strategies are accordingly proposed to collaboratively solve the trade-offs on inter-core communication, application performance, chip temperature, and system energy-efficiency in different design phases and aspects. Experimental results show that, FoToNoC can improve as large as 36.85 % on application performance, save up to 30.35 % on system energy consumption and reduce chip peak temperature by 4.1 1 ∘ C on average compared with traditional techniques. Furthermore, due to the heterogeneous core organization and the fine-grained optimization on energy-efficiency in QcNoC, averagely 18.40 % reduction on system energy consumption can be achieved with an average 2.2 4 ∘ C reduction on chip peak temperature compared with that in FoToNoC. We further demonstrate the practicality and the effectiveness of the proposed methods by case studies on real-world applications including the industry standard H. 264 decoder and DSP-stone benchmarks.

We propose a novel hardware and software co-exploration framework for efficient neural architecture search (NAS). Different from existing hardware-aware NAS which assumes a fixed hardware design and explores the neural architecture search space only, our framework simultaneously explores both the architecture search space and the hardware design space to identify the best neural architecture and hardware pairs that maximize both test accuracy and hardware efficiency. Such a practice greatly opens up the design freedom and pushes forward the Pareto frontier between hardware efficiency and test accuracy for better design tradeoffs. The framework iteratively performs a two-level (fast and slow) exploration. Without lengthy training, the fast exploration can effectively fine-tune hyperparameters and prune inferior architectures in terms of hardware specifications, which significantly accelerates the NAS process. Then, the slow exploration trains candidates on a validation set and updates a controller using the reinforcement learning to maximize the expected accuracy together with the hardware efficiency. Experiments on ImageNet show that our co-exploration NAS can find the neural architectures and associated hardware design with the same accuracy, 35.24% higher throughput, 54.05% higher energy efficiency and 136x reduced search time, compared with the state-of-the-art hardware-aware NAS., 10 pages

Neural Architecture Search (NAS), that automatically identifies the best network architecture, is a promising technique to respond to the ever-growing demand for application-specific Artificial Intelligence (AI). On the other hand, a large number of research efforts have been put on implementing and optimizing AI applications on the hardware. Out of all leading computation platforms, Field Programmable Gate Arrays (FPGAs) stand out due to its flexibility and versatility over ASICs and its efficiency over CPUs and GPUs. To identify the best neural architecture and hardware implementation pair, a number of research works are emerging to involve the awareness of hardware efficiency in the NAS process, which is called "hardware-aware NAS". Unlike the conventional NAS with a mono-criteria of accuracy, hardware-aware NAS is a multi-objective optimization problem, which aims to identify the best network and hardware pair to maximize accuracy with guaranteed hardware efficiency. Most recently, the co-design of neural architecture and hardware has been put forward to further push forward the Pareto frontier between accuracy and efficiency trade-off. This paper will review and discuss the current progress in the neural architecture search and the implementation on hardware.

System-level thermal management techniques normally map applications on non-adjacent cores to guarantee the safe temperature in many-core systems, while the communication efficiency will be oppositely affected by long-distance data transmission over conventional Network-on-Chips (NoC). SMART NoC has enabled single-cycle multi-hop bypass channels between distant cores, which can significantly reduce inter-processor communication latency. However, communication efficiency of SMART will be significantly diminished by express bypass break due to communication conflict. In order to achieve communication optimization with guaranteed system thermal reliability, we propose a dynamic reconfiguration method for logical interconnection topology through task mapping on top of SMART NoC. Active cores are physically decentralized on chip for better heat dissipation, while communication overhead can be reduced by minimized communication conflict and maximized bypass routing. Applicability and effectiveness of the proposed technique can be improved with significant achievements in reducing communication overhead and improving application performance, compared with state-of-the-art techniques.

Background Suo Quan Wan (SQW) is an effective traditional Chinese prescription on treated lower urinary tract symptoms (LUTS), and has been proved have modulation effect on the expression of transient receptor potential vanilloid 1 (TRPV1) in accordance with the recovery of bladder function of overactive bladder rat. This study further investigated the mechanism of SQW modulated TRPV1 signaling and bladder function using TRPV1 knockout (KO) mice. Methods Study was conducted using wild type and TRPV1 KO mice. The KO animals were grouped into KO group and SQW treated group. We applied in vivo cystometrogram recording techniques to analyze voiding control of the urinary bladder, as well as in vitro organ bath to study bladder distension response to various compounds, which subsequently elicited normal smooth muscle excitation. Real-time polymerase chain reaction and western blot analysis were performed to quantify the expression of TRPV1 and P2X3 in the bladder. ATP released from bladder strips was measured using the luciferin–luciferase ATP bioluminescence assay kit. Results KO preparation inhibited decrease micturition times, while micturition interval and volume were increased. Results of urodynamic record of the TRPV1−/− mice during NS infusion showed reduced bladder pressure and contraction which exhibited decreased response to α, β-me ATP, KCl, and carbachol and no response to CAP. The ATP released by the TRPV1−/− mice from strips of bladder smooth muscles was significantly reduced, along with no TRPV1 expression and reduced expression level of P2X3 in the bladder. SQW could increase ATP release in some degree, while had no effect on TRPV1 and P2X3 expression. SQW could improve bladder pressure slightly, while make no significantly effects on the force response to α,β-meATP, CAP, carbachol in gradient concentration, and KCl, as well as MBC and voiding activities. Conclusions TRPV1 plays an important role in urinary bladder mechanosensitivity. The effective SQW is hard to play its proper role on bladder function of mice without TRPV1. Electronic supplementary material The online version of this article (doi:10.1186/s12906-016-1420-6) contains supplementary material, which is available to authorized users.

Psoriasis is a chronic inflammatory skin disease that involves the induction of T-helper 1 (Th1) and T-helper 17 (Th17) cell responses and the aberrant expression of proinflammatory cytokines, including IL-1β. Copious evidence suggests that abnormal activation of Toll-like receptors (TLRs) contributes to the initiation and maintenance of psoriasis. We have evaluated an antagonist of TLR7, 8, and 9 as a therapeutic agent in an IL-23-induced psoriasis model in mice. Psoriasis-like skin lesions were induced in C57BL/6 mice by intradermal injection of IL-23 in the ear or dorsum. IL-23-induced increase in ear thickness was inhibited in a dose-dependent manner by treatment with antagonist. Histological examination of ear and dorsal skin tissues demonstrated a reduction in epidermal hyperplasia in mice treated with the antagonist. Treatment with antagonist also reduced the induction of Th1 and Th17 cytokines in skin and/or serum, as well as dermal expression of inflammasome components, NLRP3 and AIM2, and antimicrobial peptides. These results indicate that targeting TLR7, 8, and 9 may provide a way to neutralize multiple inflammatory pathways that are involved in the development of psoriasis. The antagonist has the potential for the treatment of psoriasis and other autoimmune diseases.

Non-Volatile Memory (NVM) is becoming an attractive candidate to be the swap area in embedded systems for its near-DRAM speed, low energy consumption, high density, and byte-addressability. Swapping data from DRAM out to NVM, however, can cause large performance/energy penalty and deplete the lifetime of NVM. Traditional swap mechanisms may need to be re-studied. Even through there are several swap mechanisms proposed for the hybrid DRAM-NVM systems, most of them have limited performance without considering the data access features of applications. In this paper, we analyze the data accesses features of different applications. Then, a swap mechanism, called Refinery Swap, is proposed to improve the performance of the system, reduce energy consumption, and increase the lifetime of NVM simultaneously. Refinery Swap presented two algorithms to exploit the data access features of applications and the characteristics of different kinds of memory medias. The swap operations in the system and the writes upon NVM are reduced using Refinery Swap. Extensive experiments are conducted with standard benchmarks. The experimental results show that the lifetime of NVM for the system with Refinery Swap can be 83 times that of Linux Swap. The performance of the system with Refinery Swap can be 17 times that of DR.Swap, the state-of-the-art swap mechanism for hybrid memory embedded systems. Moreover, the energy consumption of the system achieves 17 times lower.

In this dark silicon era, techniques have been developed to selectively activate nonadjacent cores in physical locations to maintain the safe temperature and allowable power budget on a many-core chip. This will result in unexpected increase in the communication overhead due to longer average distance between active cores in a typical mesh-based Network-on-Chip (NoC), and in turn reduce the system performance and energy efficiency. In this paper, we present FoToNoC, a Folded Torus-like NoC, and a hierarchical management strategy on top of it, to address this tradeoff problem for heterogeneous many-core systems. Optimizations of chip temperature, inter-core communication, application performance, and system energy consumption are well isolated in FoToNoC, and addressed in different design phases and aspects. A cluster-based hierarchical strategy is proposed to manage the system adaptively in several different control levels. Compared with mesh-based systems on a set of synthetic and real benchmarks, FoToNoC can achieve on average 39.4% performance improvement when similar temperature conditions are maintained, and the proposed strategy can further reduce the total energy consumption by up to 42.0%.

Network on Chip (NoC) has become a promising solution for the communication paradigm of the next-generation multiprocessor system-on-chip (MPSoC). As communication has become an integral part of on-chip computing, researchers are paying more attention to its implementation and optimization. Traditional techniques that model inter-processor communication inaccurately will lead to unexpected runtime performance, which is on average 90.8% worse than the predicted results based on an observation. In this paper, we present an application mapping and scheduling technique for NoC-based MPSoCs that integrates fine-grain optimization on inter-processor communications with the objective of minimizing the schedule length. A communication model is proposed to address properly the latency of inter-processor communication with network contention. Performance evaluation results show that solutions obtained by the proposed technique can generate realistic performance that is on average 34.7% higher than traditional techniques, and the Integer-Linear Programming (ILP) based approach can outperform the state-of-the-art heuristic algorithms by 31.1%. A case study on H.264 HDTV decoder shows that our approach achieves 22.8% improvement in prediction accuracy, 20.9% improvement in performance and 40% reduction in the number of network contentions.

To satisfy the ever increasing performance requirement of applications, Multiprocessor System-on-Chip (MPSoC) plays an irreplaceable role in embedded system these days. It is significant to effectively optimize communication for achieving maximum parallelism on MPSoC, especially on Network-on-Chip (NoC) based architectures. The problem of how to make an arbitration of communication congestion is remained unsolved. In this paper, we propose a reasonable Unified Priority-Based Scheduling (UPS) algorithm for task and communication co-scheduling with communication contention, which is based on a novel Task Communication Graph (TCG) model of an application. The proposed method is more accurate and effective to describe the overall process of applications. The experimental results show that the performance is improved by 31.1% on average of scheduling generated by our algorithm. It verifies that the proposed method in this paper can improve the performance of contention-aware task and communication scheduling on NoC-based MPSoC architecture.

With the increasing power density and numberof cores integrated into a single chip, thermal managementis widely recognized as one of the essential issues in Multi-Processor Systems-on-Chip (MPSoCs). An uncontrolled temperaturecould significantly decrease system performance, leadto high cooling and packaging costs, and even cause seriousdamage. These issues have made temperature one of themajor factors that must be addressed in MPSoC designs. Static scheduling of applications should take the thermaleffects of task executions into consideration to keep the chiptemperature under a safety threshold. However, inaccuratetemperature estimation would cause processor overheating orsystem performance degradation. In this paper, we proposean improved thermal modeling technique that can be used topredict the chip temperature more accurately and efficiently atdesign time. We further develop a simulated annealing (SA)-based algorithm to address the static application mapping andscheduling problem based on the improved thermal model. Thethermal condition is greatly improved and the total energyconsumption is minimized. Experimental results show thatthe improved thermal modeling technique could provide anaverage of over 99% accuracy of temperature prediction whencomparing with the results offered by Hotspot simulations. Based on it, the SA-based algorithm could reduce the chancesthat the temperature threshold to be violated at runtime by24.3%.

High mobility group protein 1 (HMGB1) is a non-histone nuclear protein with a dual function. Inside the cell, HMGB1 binds to DNA and modulates a variety of processes, including transcription. Outside the cell, HMGB1 can serve as an alarmin to mediate disease manifestations in animal models of sepsis and arthritis; in these models, blocking HMGB1 can attenuate disease.1–3 In in vitro experiments, HMGB1 translocation and cellular release can occur during activation as well as cell death and is present in tissue in conditions, such as rheumatoid arthritis and cutaneous lupus.4 5 While original studies suggested that release occurs only with necrosis, …

High-mobility group protein 1 (HMG1) is a nonhistone nuclear protein that is a prototype of a dual-function alarmin whose immune activity is dependent upon its cellular location. Inside the cell, HMG1 binds to DNA and has a role in transcriptional regulation. Outside the cell, HMG1 acts as a cytokine and has activities that resemble those of tumor necrosis factor. The cytokine activities of HMG1 become manifest when this protein translocates from the nucleus to the cytoplasm and, eventually, into the external milieu; this translocation occurs during cell activation and cell death. Given its cytokine activity, HMG1 has been implicated in the pathogenesis of a broad range of immune-mediated diseases including arthritis. The role for this protein in arthritis was established by observations of the expression of HMG1 in synovial tissue of patients with rheumatoid arthritis as well as in the joints of animals used to model arthritis. Furthermore, in the mouse model of collagen-induced arthritis, treatment with antibodies to HMG1 or to an inhibitory domain of HMG1 can attenuate joint inflammation and damage. These studies identify a novel pathway in the pathogenesis of inflammatory arthritis, as well as a new target for biologic therapy.