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A method is proposed for computing with unreliable nanoscale devices that have a high rate of transient errors. Errors are corrected using a probabilistic circuit in which device noise is leveraged as a computational asset. Example designs that achieve a low output bit error probability are presented. The effect of permanent defects is also evaluated, and transient device noise is found to be beneficial for correcting hard defects for defect rates of as high as 0.1% and transient fault rates above 1%. When compared with existing fault-tolerant methods, the sample design requires considerably fewer redundant gates to achieve reliable operation. These results predict that some degree of engineered randomness may prove to be a useful signal-processing feature in future nanoelectronic systems. Index Terms--Error-correction, fault-tolerance, faulty gates, low-density parity-check (LDPC) codes, reliable computation.

A built-in serf-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation. Index Terms--Error-control codes, low-density parity check (LDPC) codes, factor graphs, analog decoding, built-in self-test (BIST), message passing.

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented. Index Terms--Analog decoding, iterative decoding, low-density parity check (LDPC) decoder, low voltage, low power, Turbo decoder.

Laser-induced breakdown spectroscopy (LIBS) of metal-seeded aerosols and a hydrocarbon flame were studied to determine the proper experimental condition for rocket motor application. LIBS and atomic emission spectroscopy (AES) were also performed in the rocket motor simulator to evaluate both technologies for the health monitoring of the rocket engine. The LIBS signal of the seeded element goes down drastically in the presence of the flame in comparison to the signal obtained from the aerosols of the elements. Similarly the LIBS signal of the trace elements was very weak in the luminous flame and the simulator plume in comparison to the measurement outside it. The intensity of the LIBS signal from the trace elements present in the plume/flame was found to be dependent on the process of seeding, the transition probability, and the decay time of the background emission. Ultimately LIBS was found to be more sensitive than AES in detecting the trace elements in the simulator plume. This study establishes LIBS as an improved health-monitoring system over AES for the plume studied.