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This paper proposes the architecture of the hash accelerator, developed in the framework of the European Processor Initiative. The proposed circuit supports all the SHA2 and SHA-3 operative modes and is to be one of the hardware cryptographic accelerators within the crypto-tile of the European Processor Initiative. The accelerator has been verified on a Stratix IV FPGA and then synthesised on the Artisan 7 nanometres TSMC silicon technology, obtaining throughputs higher than 50 Gbps for the SHA2 and 230 Gbps for the SHA-3, with complexity ranging from 15 to about 30 kGE and estimated power dissipation of about 13 (SHA2) to 26 (SHA-3) mW (supply voltage 0.75 V). The proposed design demonstrates absolute performances beyond the state-of-the-art and efficiency aligned with it. One of the main contributions is that this is the first SHA-2 SHA-3 accelerator synthesised on such advanced technology.

This paper describes the FPGA based verification platform that is dedicated to improve student efficiency for the course on Digital Design with FPGAs. We developed a functional verification platform that extends the number of I/O devices, which is usually limited on development kits. Simple PicoBlaze CPU-based design is used to synchronize the input and output signals between PC and the FPGA. Complete verification platform occupies only 14% of the Spartan 3 XC3S200 FPGA device. During the course, students get the knowledge about the PicoBlaze CPU and it's assembly language, as well as getting familiar with the FPGAs and VHDL. At the end of the lectures, students are able to understand the HW/SW co-design and to use the verification platform for making their final project.