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OBJECTIVES RNASEH1 gene has recently been associated with type 1 diabetes (T1D) in Colombia. The purpose of this study was to fine mapping the putative functional variant in RNASEH1 and testing its interaction with HLA tagSNPs. METHODS Two-hundred nuclear families with T1D were included in this study. Probands were tested for GAD65 and IA-2 autoantibodies. Genotyping was performed using 20 coding tagSNPs uncovered through Sanger sequencing (N = 96), in addition to 23 tagSNPs chosen from 1000genomes to cover the extent of the gene region. Also, 45 tagSNPs for classic HLA alleles associated with T1D were also genotyped. The transmission disequilibrium test (TDT) was used to test for association and a multiple testing correction was made using permutation. Interaction between RNASEH1 variants and HLA was evaluated by means of the M-TDT test. RESULTS We identified 20 variants (15 were novel) in the 96 patients sequenced. None of these variants were in linkage disequilibrium. In total, 43 RNASEH1 variants were genotyped in the 200 families. Association between T1D and rs7607888 was identified (P = .002). Haplotype analysis involving rs7607888 variant revealed even stronger association with T1D (most significative P = .0003). HLA tagSNPs displayed stronger associations (OR = 6.39, 95% CI = 4.33-9.44, P-value = 9.74E-28). Finally, we found several statistically significant interactions of HLA variants with rs7607888 (P-value ranged from 8.77E-04 to 5.33E-12). CONCLUSION Our results verify the association of rs7607888 in RNASEH1 gene with T1D. It is also shown in the interaction between RNASEH1 and HLA for conveying risk to T1D in Northwest Colombia. Work is underway aiming to identify the actual classic HLA alleles associated with the tagSNPs tested here.

Visual Simultaneous Localization and Mapping (SLAM) technologies based on point features achieve high positioning accuracy and complete map construction. However, despite their time efficiency and accuracy, such SLAM systems are prone to instability and even failure in poor texture environments. In this paper, line features are integrated with point features to enhance the robustness and reliability of stereo SLAM systems in poor texture environments. Firstly, method Edge Drawing lines (EDlines) is applied to reduce the line feature detection time. Meanwhile, the proposed method improves the reliability of features by eliminating outliers of line features based on the entropy scale and geometric constraints. Furthermore, this paper proposes a novel Bags of Word (BoW) model combining the point and line features to improve the accuracy and robustness of loop detection used in SLAM. The proposed PL-BoW technique achieves this by taking into account the co-occurrence information and spatial proximity of visual words. Experiments using the KITTI and EuRoC datasets demonstrate that the proposed stereo Point and EDlines SLAM (PEL-SLAM) achieves high accuracy consistently, including in challenging environments difficult to sense accurately. The processing time of the proposed method is reduced by 9.9% and 4.5% when compared to the Point and Line SLAM (PL-SLAM) and Point and stereo Point and Line based Visual Odometry (sPLVO) methods, respectively.

Object extraction is an important tool in many applications within the image processing and computer vision communities. You Only Look Once version 3 (YOLOv3) has been extensively applied to many fields as a state-of-the-art technique for object semantic detection. Despite its numerous characteristics, YOLOv3 has to be combined with appropriate image segmentation technologies to achieve effective 2D object extraction in real-time monitoring, robot navigation, and target search. In this article, the K-means algorithm is applied to the segmentation of depth images. Considering the inherent sensitivity to the randomness of the initial cluster center and the uncertainty of cluster number K in the initialization phase of the K-means algorithm, this article proposes a new method that combines the semantic image information with the image depth information. Specifically, this method proposed to pre-classify the center depth of the object to determine the appropriate value of K required in the K-means algorithm. At the same time, the proposed algorithm improves the selection of the initial center via the maximin method. This article introduces a multi-parameter extraction method to enable to correctly identify the object of interest after image segmentation. The technique considers three parameters to achieve this: i) the elements of size, ii) the connected domain, and iii) the diagonal detection. Experiments using open-source datasets demonstrate that the average processing time and the segmentation accuracy of the improved K-means algorithm are 20.36% faster and 3.12% higher than the conventional K-means algorithm, respectively. The extraction accuracy of the proposed method is 6.69% higher than that of the SuperCut extraction method.

Hybrid aircraft are systems capable of flying as either fixed-wing aircraft or rotorcraft, as well as transition between these modes. Nowadays, hybrid aircraft have many potential applications as t...

Video sharing (e.g., YouTube, Vimeo, Facebook, TikTok) accounts for the majority of internet traffic, and video processing is also foundational to several other key workloads (video conferencing, virtual/augmented reality, cloud gaming, video in Internet-of-Things devices, etc.). The importance of these workloads motivates larger video processing infrastructures and – with the slowing of Moore’s law – specialized hardware accelerators to deliver more computing at higher efficiencies. This paper describes the design and deployment, at scale, of a new accelerator targeted at warehouse-scale video transcoding. We present our hardware design including a new accelerator building block – the video coding unit (VCU) – and discuss key design trade-offs for balanced systems at data center scale and co-designing accelerators with large-scale distributed software systems. We evaluate these accelerators “in the wild" serving live data center jobs, demonstrating 20-33x improved efficiency over our prior well-tuned non-accelerated baseline. Our design also enables effective adaptation to changing bottlenecks and improved failure management, and new workload capabilities not otherwise possible with prior systems. To the best of our knowledge, this is the first work to discuss video acceleration at scale in large warehouse-scale environments.

At present, most of the current Simultaneous Localization and Mapping (SLAM) algorithms are limited to work in static environments. However, the world is not static and dynamic objects are typically present in the environments, leading to the failure of the general SLAM. In this paper, a dynamic object removal method combining semantic detection with depth image segmentation is proposed and applied in the real-time SLAM library for cameras ORB-SLAM2 system to achieve robust RGB-D SLAM for dynamic environments. In the proposed method, the potential dynamic regions are captured via YOLOv4 and K-means image segmentation. Different from the general purposes of processing dynamic regions, the potential dynamic regions are redetected by dynamic outliers rejection, which improves the reliability of dynamic object removal. Experiments using the TUM RGB-D dataset demonstrate that the proposed method performs with increased robustness and accuracy when compared to the original ORB-SLAM2 without dynamic object removal in dynamic environments.

Healthcare is considered as one of the most promising application areas for artificial intelligence and analytics (AIA) just after the emergence of the latter. AI combined to analytics technologies is increasingly changing medical practice and healthcare in an impressive way using efficient algorithms from various branches of information technology (IT). Indeed, numerous works are published every year in several universities and innovation centers worldwide, but there are concerns about progress in their effective success. There are growing examples of AIA being implemented in healthcare with promising results. This review paper summarizes the past 5 years of healthcare applications of AIA, across different techniques and medical specialties, and discusses the current issues and challenges, related to this revolutionary technology. A total of 24,782 articles were identified. The aim of this paper is to provide the research community with the necessary background to push this field even further and propose a framework that will help integrate diverse AIA technologies around patient needs in various healthcare contexts, especially for chronic care patients, who present the most complex comorbidities and care needs.

Digital holographic microscopy is well suited to the search for microbial species due in part to its intrinsic stability, volumetric imaging capability, and sensitivity to very dilute samples. This is all done with a system having no moving parts, making it additionally attractive for flight instrumentation. Our devices have been field tested on several occasions, and have demonstrated robustness to extreme conditions. When bacteria are alive and moving, they are easy to detect. However, some measurements are subtler. Can we distinguish between a live yet nonmotile species and a mineral, for instance? To provide another method of discrimination, we have added the ability to measure object polarization. This will allow us to characterize the sample by polarization state without any sacrifice in the spatial or temporal resolution (

This paper presents vbench, a publicly available benchmark for cloud video services. We are the first study, to the best of our knowledge, to characterize the emerging video-as-a-service workload. Unlike prior video processing benchmarks, vbench's videos are algorithmically selected to represent a large commercial corpus of millions of videos. Reflecting the complex infrastructure that processes and hosts these videos, vbench includes carefully constructed metrics and baselines. The combination of validated corpus, baselines, and metrics reveal nuanced tradeoffs between speed, quality, and compression. We demonstrate the importance of video selection with a microarchitectural study of cache, branch, and SIMD behavior. vbench reveals trends from the commercial corpus that are not visible in other video corpuses. Our experiments with GPUs under vbench's scoring scenarios reveal that context is critical: GPUs are well suited for live-streaming, while for video-on-demand shift costs from compute to storage and network. Counterintuitively, they are not viable for popular videos, for which highly compressed, high quality copies are required. We instead find that popular videos are currently well-served by the current trajectory of software encoders.

The Collaborative Learning of Usability Experiences (CLUE) training program1 is an NSERC CREATE grant that trains Canada's leaders in HCI. We aim to improve our trainees' capabilities across the disciplinary boundaries (Information Technology, Psychology, Computer Science, and Design), through collaborative professional skills development, experiential learning, and technical skills. Within human computer interaction (HCI), usability professionals employ research-based methods and principles to understand users’ conceptual models of tasks and design interfaces and experiences accordingly. There is an increased demand for skills in usability experience (UX) design and testing, yet we identify a lack of training in these skills in current graduate programs across Canada. Even in the context of multidisciplinary HCI programs, graduates often face a usability knowledge gap, which may be due to a lack of grounding in real-world contexts, without business constraints.

The purpose of this research is to validate user’s satisfaction with the human resources management model based on Business Intelligence. It is said that BI solutions support in deciding in different types of areas, especially in personnel management, which have to consider the analysis of human talent, skills acquired, and the necessary budget to provide a new specialty referring to the work that will be perform. The method of the purpose is the integration of the financial, personnel management, organization chart and finally the organizational culture components. In the last component there are important factors to enhance the human talent of the organization, which are the values, awareness and work climate perceived by each person. The experiment was conducted with surveys of twenty managers to measure their level of satisfaction in aspects of management, design, and efficiency in deciding. The results in general were high satisfaction of the users in the experience they had with the BI solution by three different types of reports developed with support of the Microsoft Power BI tool.

The evolution in the missions rsquo complexity of both military aircraft and Unmanned Aerial Vehicles UAVs and the increase in civilian air traffic with limited runways have led to the development of a new category of aircraft called Transitional Aircraft TA The goal of TA is to take advantages of both the characteristics of fixed wing aircraft like high speed range and endurance and of rotorcraft such as hovering low speed flight and Vertical Take off and Landing VTOL Despite the abundant knowledge on designing both fixed wing aircraft and rotorcraft designing TA has proven to be a challenging process and poorly understood Currently there is no well accepted generic methodology that can be used for designing this type of aircraft such as tiltrotor systems due to the fact that there are numerous challenges regarding the selection of the proper TA configuration Although somewhat effective previously developed TA suffer from problems regarding the mutual aerodynamic interaction that occurs during the transition flight phase when the aircraft transitions between fixed wing and rotorcraft flight modes In order to cope with these problems this paper presents a preliminary design methodology for TA with a set of newly developed mathematical formulations that integrate traditional fixed wing and rotorcraft aircraft design methodologies into a comprehensive TA design methodology Due to the potential large set of TA configurations that exist and can be proposed this paper focuses on transitional tiltrotors which have been identified as critical importance The proposed TA design approach is used to analyze a hypothetical TA configuration under development by the authors of this paper showing that the proposed design approach can be used to prevent some of the frequent shortcomings found on previously developed aircraft The methodology is able to assist TA designers obtain adequate power wing and rotor disc loadings using the developed sizing mathematical formulations for tiltrotor aircraft based on integrating the performance requirements in the fixed wing rotorcraft and transition flying modes

It is widely accepted that future HPC systems will be limited by their power consumption. Current HPC systems are built from commodity server processors, designed over years to achieve maximum performance, with energy efficiency being an after-thought. In this paper we advocate a different approach: building HPC systems from low-power embedded and mobile technology parts, over time designed for maximum energy efficiency, which now show promise for competitive performance. We introduce the architecture of Tibidabo, the first large-scale HPC cluster built from ARM multicore chips, and a detailed performance and energy efficiency evaluation. We present the lessons learned for the design and improvement in energy efficiency of future HPC systems based on such low-power cores. Based on our experience with the prototype, we perform simulations to show that a theoretical cluster of 16-core ARM Cortex-A15 chips would increase the energy efficiency of our cluster by 8.7×, reaching an energy efficiency of 1046 MFLOPS/W.

GPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. However GPUs do not provide the support for resource sharing traditionally expected in these scenarios. Thus, such systems are unable to provide key multiprogrammed workload requirements, such as responsiveness, fairness or quality of service. In this paper, we propose a set of hardware extensions that allow GPUs to efficiently support multiprogrammed GPU workloads. We argue for preemptive multitasking and design two preemption mechanisms that can be used to implement GPU scheduling policies. We extend the architecture to allow concurrent execution of GPU kernels from different user processes and implement a scheduling policy that dynamically distributes the GPU cores among concurrently running kernels, according to their priorities. We extend the NVIDIA GK110 (Kepler) like GPU architecture with our proposals and evaluate them on a set of multiprogrammed workloads with up to eight concurrent processes. Our proposals improve execution time of high-priority processes by 15.6x, the average application turnaround time between 1.5x to 2x, and system fairness up to 3.4x. We would like to thank the anonymous reviewers, Alexan- der Veidenbaum, Carlos Villavieja, Lluis Vilanova, Lluc Al- varez, and Marc Jorda on their comments and help improving our work and this paper. This work is supported by Euro- pean Commission through TERAFLUX (FP7-249013), Mont- Blanc (FP7-288777), and RoMoL (GA-321253) projects, NVIDIA through the CUDA Center of Excellence program, Spanish Government through Programa Severo Ochoa (SEV-2011-0067) and Spanish Ministry of Science and Technology through TIN2007-60625 and TIN2012-34557 projects.

Increasingly complex space operations require novel advanced structural composites for reconfigurable spacecrafts to have excellent flexural strength in reconfiguration processing and orbital maneuvering. Functionalized multiwalled carbon nanotubes (MWCNTs) are performed to fabricate the MWCNTs/carbon fiber/N, N′-4, 4′-bimaleimide diphenyl methane/diallylbisphenol A (MWCNTs/CF/BMI/DBA) composites. ANSYS analysis reveals that the requiring lowest flexural strength of the composites is 1,150 MPa to meet actual requirements. The flexural strength of the MWCNTs/CF/BMI/DBA composites with 1 wt% functionalized MWCNTs can fully meet the actual use for reconfigurable spacecrafts. And the thermal stabilities of the MWCNTs/CF/BMI/DBA composites are increased with the increasing addition of MWCNTs. POLYM. COMPOS., 35:2018–2022, 2014. © 2014 Society of Plastics Engineers

UNAM is the oldest and one of the most prestigious universities in the Americas. The main campus of the university is home of about 300 000 students and covers an area of about 4 square-kilometres in the south of Mexico City. UNAM is also one of the biggest electricity consumers in Mexico-City. More than 70 Million kWh electricity are consumed yearly, producing about 49 000 tons of CO2 emission. Within the paper we will show that this could be changed with a high financial and educational profit. As UNAM has no heating and only a few cooling systems, lighting is by far the biggest use of electricity. The existing lighting system is extremely inefficient while providing unsatisfactory illumination in some places. The UNEP Centre on Sustainable Production and Consumption (CSCP) together with Buro O-quadrat devised a project which demonstrates how UNAM can benefit from an upgrade to a highly efficient lighting system. What makes the project unique is that the results are not based on theoretical calculations but were corroborated by implementation results of a highly efficient lighting system in four different areas (a foyer, classrooms, a library and a workshop) and the measurement of the electricity savings. Within these four areas the average electricity saving was 84% and the combined pay-back time was 2.7 years. Based on the empirical results and an analysis of 10 UNAM-buildings a master plan was developed for the entire university campus. Here the objective was to establish the broad strategic principles for a successful lighting system upgrade, as well as the necessary budget and savings that could be achieved. The results demonstrate that an initial investment of US$ 14 million would result in electricity costs savings of US$ 68 million over the 20 year lifetime of the upgraded lighting system. About thirty per cent of the electricity consumed in UNAM today could be saved with a high profit on investment. In a second step we show that most of the remaining electricity consumption could be produced by solar energy. The Feed-in Tariff system in Germany has led to a high capacity of PV-production and lowered the cost for PV-systems: In May 2013 a 40 kW PV system, including all parts for the mounting, can be bought in Europe for a price of about 800 Euro/kW. Assuming that on 2% of the UNAM-area PV-systems would be installed, these systems could produce about 23 GWh with lower costs compared to the electricity price UNAM has to pay. Combining the investment for efficient lighting and PV-systems, about 60% (or about 29 000 tons) of the CO2-emissions of UNAM could be saved with a high rate of return. Best of all: What would be a more convincing way to educate 60 000 students every year about sustainability than a practical example of highly efficient lighting system and powered by solar energy? UNAM could be a light house for many other universities and schools.

Design of a vision-based target tracking control strategy for a dual-rotor UAV with tilting rotors is presented. In this research, the under-study UAV is equipped with a sliding mass that can slide over a motorized linear track attached to the UAV's fuselage enabling it to perform sophisticated maneuvers by monitoring its five controllable degrees of freedom. The dynamic model of the system is first derived and then a model-based controller using vision based pose estimation, obtained via an onboard down-looking camera, is designed enabling the UAV to: (1) pitch hover in position, (2) servo towards a target position, and (3) track a moving target. Simulations show the premise of the proposed vision-based control strategy.

Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution.

PurposeThe blogosphere is an active arena for the communication of topic‐area claims by marketer and non‐marketer sources. Determinants of influence in the blogosphere have not been well documented. The purpose of this paper is to investigate trust in bloggers, in a framework involving characteristics of bloggers and blogs and blog reading outcomes.Design/methodology/approachBlog‐reader perceptions of bloggers and blogs are derived and tested on a sample of blog readers for their effects on trust formation. Tests of mediation examine the role of perceived personal outcomes of blog reading in trust‐formation processes.FindingsTrust formation is predicted by engagement knowledge of the blogger, unique reading experiences, and belief that the blog improved the marketspace. Blogger authoritative knowledge negatively impacted trust intentions. Positive experiences from blog reading mediate relationships between blog and blogger characteristics and intentions to trust.Research limitations/implicationsBlog readers examined in this initial investigation may not be totally representative of the general population of blog readers. Replications with other populations are needed.Practical implicationsThe paper's findings suggest knowledge is an essential characteristic of a trustworthy blogger, but knowledge unrelated to everyday information needs holds little perceived value for readers. Firms operating blogs may wish to de‐emphasize their topic‐area authoritative knowledge and project a voice of topic‐area engagement.Originality/valueThe paper identifies salient trust‐related blogger and blog characteristics and provides an indication of a domain‐specific trust‐development process that is applicable to marketer and non‐marketer information sources.

Many Minority Serving Institutions (MSI) in the United States lack sufficient resources and knowledge to take significant advantage of the national and international computational resources available to advance computational science research and education. National challenges raised for Homeland Security (HS) have focused US government attention on the critical yet untapped human resource potential at MSIs. The US National Science Foundation’s TeraGrid has attempted to define, promote and deliver an integrated set of high performance computing resources to the national academic research community. However, a gap persists in the connections between the TeraGrid program and non-TeraGrid national computational resources and data. For MSIs and other users, these circumstances hinder seamless, natural use of resources from local, campus infrastructure through national high performance computing research tools. In spite of impressive TeraGrid advances, its user community falls short of engaging a much broader potential community especially the MSI community. A campus-based integrated CyberInfrastructure (CI) is essential to bridge this gap.

This article investigates the relationship of learning and its infrastructure using Web 2.0 technologies to facilitate the acquisition of skills needed to succeed in a global economy. We explore the learning phenomenon as a way to bring forward a process of continuous improvement supported by social software. We use a commonly accepted definition of learning to evaluate different learning theories, since it seems that the definition of learning itself is not a major source of difference between learning theories. Their differences are over issues of interpretation, not over definition. The theories reviewed are used in the design of a framework to assess the infrastructure against expectations of skill proficiency using Web 2.0 tools, i.e., wikis, blogs, social bookmarking, tagging, etc. which must emerge as a result of registering in an introduction to business information and communication technologies (ICT) course in a Canadian university. In this course, we use Friedman’s (The world is flat: a brief history of the twenty-first century release 3.0, Picador, New York, 2007) thesis that the “world is flat” to discuss issues of globalization and the role of ICT. Students registered in the course are usually familiar with some of the tools we introduce and use in the course. The students are members of Facebook or MySpace, regularly check YouTube, and use Wikipedia in their studies. These tools are the tools to socialize. In our course, we broaden the students’ horizons and explore the potential business benefits of such tools and empower the students to use Web 2.0 technologies within a business context.

Current multicore architectures offer high throughput by increasing hardware resource utilization. As the number of cores in a multicore system increases, providing Quality of Service (QoS) to applications in addition to throughput is becoming an important problem. In this work, we present FlexDCP, a framework that allows the Operating System (OS) to guarantee a QoS for each application running in a chip multiprocessor. FlexDCP directly estimates the performance of applications for different cache configurations instead of using indirect measures of performance like the number of misses. This information allows the OS to convert QoS requirements into resource assignments. Consequently, it offers more flexibility to the OS as it can optimize different QoS metrics like per-application performance or global performance metrics such as fairness, weighted speed up or throughput. Our results show that FlexDCP is able to force applications in a workload to run at a certain percentage of their maximum performance in 94% of the cases considered, being on average 1:48% under the objective for remaining cases. When optimizing a global QoS metric like fairness, FlexDCP consistently outperforms traditional eviction policies like LRU, pseudo LRU and previous dynamic cache partitioning proposals for two-, four- and eightcore configurations. In an eight-core architecture FlexDCP obtains a fairness improvement of 10:1% over Fair, the best policy in the literature optimizing fairness.

Energy efficiency is one of the key challenges in high-performance computing (HPC). The current target of 1 ExaFlop in 20 MW requires a ten-fold improvement in energy efficiency, which is only possible through significant improvements in the energy efficiency throughout the system. Interconnects are particularly inefficient, since their links are always on, consuming full power in order to provide low latency, even though the average interconnect utilization is low. To address the above, the Ethernet standards committee in-charge of 40/100/400Gb Ethernet has opted to include protocols that define low power modes, specifically Fast-Wake, alongside the older Deep-Sleep, to make interconnect links energy proportional. With these standards ratified as recently as March 2014, it is unclear how these low power modes can be used in HPC. While energy efficiency is critical, techniques with excessive performance overheads are unlikely to be adopted in HPC. To this end, this paper performs the first detailed analysis of Fast-Wake mode for link energy savings in the context of HPC. Our results show that a combination of Fast-Wake and Deep-Sleep can reduce link energy savings by up to 70% with less than 1% performance overheads. However, we show how the parameters of these low power modes must be carefully configured to obtain the right trade-offs in energy and performance. We believe that our analysis could benefit interconnect vendors looking to use these low power modes for deployment in HPC.

Current operating systems (OS) perceive the different contexts of simultaneous multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the same hardware resources. Furthermore, hardware resources are assigned to threads implicitly as determined by the SMT instruction fetch (Ifetch) policy, without the control of the OS. Both factors cause a lack of control over how individual threads are executed, which can frustrate the work of the job scheduler. This presents a problem for general purpose systems, where the OS job scheduler cannot enforce priorities, and also for embedded systems, where it would be difficult to guarantee worst-case execution times. In this paper, we propose a novel strategy that enables a two-way interaction between the OS and the SMT processor and allows the OS to run jobs at a certain percentage of their maximum speed, regardless of the workload in which these jobs are executed. In contrast to previous approaches, our approach enables the OS to run time-critical jobs without dedicating all internal resources to them so that non-time-critical jobs can make significant progress as well and without significantly compromising overall throughput. In fact, our mechanism, in addition to fulfilling OS requirements, achieves 90 percent of the throughput of one of the best currently known fetch policies for SMTs.

Best Student Paper Award, a la SC13: International Conference for High Performance Computing, Networking, Storage and Analysis In the late 1990s, powerful economic forces led to the adoption of commodity desktop processors in high-performance computing. This transformation has been so effective that the June 2013 TOP500 list is still dominated by x86. In 2013, the largest commodity market in computing is not PCs or servers, but mobile computing, comprising smart-phones and tablets, most of which are built with ARM-based SoCs. This leads to the suggestion that once mobile SoCs deliver sufficient performance, mobile SoCs can help reduce the cost of HPC. This paper addresses this question in detail. We analyze the trend in mobile SoC performance, comparing it with the similar trend in the 1990s. We also present our experience evaluating performance and efficiency of mobile SoCs, deploying a cluster and evaluating the network and scalability of production applications. In summary, we give a first answer as to whether mobile SoCs are ready for HPC. Peer Reviewed Award-winning

The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The limitations of traditional memory technologies are pushing research in the direction of hybrid memory systems that, besides DRAM, include one or more modules based on some of the higher-density non-volatile memory technologies, where one of them will provide the required bandwidth, while the other will provide the required capacity for the application. This creates many challenges with data placement and migration policies between the modules of such hybrid memory system. In this paper, we propose an architecture with a hybrid memory design that places two technologically different memory modules in a flat address space. On such system, we evaluate several HPC workloads against different data placement and migration policies, compare their performance by means of execution time and the number of non-volatile memory writes, and consider how it can be applied to the future HPC architectures. Our results show that the hybrid memory system with dynamic page migration and limited DRAM capacity, can achieve performance that is comparable to a hypothetical, hard to implement, DRAM-only system.

One of the greatest challenges in computer architecture is how to write efficient, portable, and correct software for multi-core processors. A promising approach is to expose more parallelism to the compiler, through the use of domain-specific languages. The compiler can then perform complex transformations that the programmer would otherwise have had to do. Many important applications related to audio and video encoding, software radio and signal processing have regular behavior that can be represented using a stream programming language. When written in such a language, a portable stream program can be automatically mapped by the stream compiler onto multicore hardware. One of the most difficult tasks of the stream compiler is partitioning the stream program into software threads. The choice of partition significantly affects performance, but finding the optimal partition is an NP-complete problem. This paper presents a method, based on Extreme Value theory (EVT), that statistically estimates the performance of the optimal partition. Knowing the optimal performance improves the evaluation of any partitioning algorithm, and it is the most important piece of information when deciding whether an existing algorithm should be enhanced. We use the method to evaluate a recently-published partitioning algorithm based on a heuristic. We further analyze how the statistical method is affected by the choice of sampling method, and we recommend how sampling should be done. Finally, since a heuristic-based algorithm may not always be available, the user may try to find a good partition by picking the best from a random sample. We analyze whether this approach is likely to find a good partition. To the best of our knowledge, this study is the first application of EVT to a graph partitioning problem.

Objective Millions of children in North America receive an annual flu vaccination, many of whom are at risk of experiencing severe distress. Millions of children also use technologically advanced devices such as computers and cell phones. Based on this familiarity, we introduced another sophisticated device – a humanoid robot – to interact with children during their vaccination. We hypothesized that these children would experience less pain and distress than children who did not have this interaction. Method This was a randomized controlled study in which 57 children (30 male; age, mean ± SD: 6.87 ± 1.34 years) were randomly assigned to a vaccination session with a nurse who used standard administration procedures, or with a robot who was programmed to use cognitive-behavioral strategies with them while a nurse administered the vaccination. Measures of pain and distress were completed by children, parents, nurses, and researchers. Results Multivariate analyses of variance indicated that interaction with a robot during flu vaccination resulted in significantly less pain and distress in children according to parent, child, nurse, and researcher ratings with effect sizes in the moderate to high range (Cohen's d = 0.49–0.90). Conclusion This is the first study to examine the effectiveness of child–robot interaction for reducing children's pain and distress during a medical procedure. All measures of reduction were significant. These findings suggest that further research on robotics at the bedside is warranted to determine how they can effectively help children manage painful medical procedures.

Energy efficiency is a first-order concern when deploying any computer system. From battery-operated mobile devices, to data centers and supercomputers, energy consumption limits the performance that can be offered.We are exploring an alternative to current supercomputers that builds on the small energy-efficient mobile processors. We present results from the prototype system based on ARM Cortex-A9 and make projections about the possibilities to increase energy efficiency.

In throughput-aware CMPs like GPUs and DSPs, software-managed streaming memory systems are an effective way to tolerate high latencies. E.g., the Cell/B.E. incorporates local memories, and data transfers to/from those memories are overlapped with computation using DMAs. In such designs, the latency of the memory system has little impact on performance; instead, memory bandwidth becomes critical. With the increase in the number of cores, conventional DRAMs no longer suffice to satisfy the bandwidth demand. Hence, recent throughput-aware CMPs adopted caches to filter off-chip traffic. However, such caches are optimized for latency, not bandwidth. This work presents a re-design of the memory system in throughput-aware CMPs. Instead of a traditional latency-aware cache, we propose to spread the address space using fine-grained interleaving all over a shared non-coherent last-level cache (LLC). In this way, on-chip storage is optimally used, with no need to keep coherency. On the memory side, we also propose the use of interleaving across DRAMs but with a much finer granularity than usual page-size approaches. Our proposal is highly optimized for bandwidth, not latency, by avoiding data replication in the LLC and by using fine-grained address space interleaving in both the LLC and the memory. For a CMP with 128 cores and 64-MB LLC, performance is improved by 21% due to the LLC optimizations and an extra 42% due to the off-chip memory optimizations, for a total 1.7 times performance improvement.

Cooperation control between human's and mobile manipulators has received big interest in the last few years. Mobile manipulators (MMs) have been suggested for various applications such as tasks involving hazardous environments, explosive handling, waste management, outdoor exploration and space operations. This paper describes a novel control algorithm for human-MM cooperation executing tasks in rough outdoor terrains. The proposed approach uses inexpensive common MM sensors such as wrist force/torque, IMU and joint/wheel encoders to achieve minimal human effort. The paper describes a control mechanism that enables ground mobile manipulators to execute complex tasks in cooperation with humans or other autonomous robots when working in unknown, dynamic heterogeneous outdoor rough terrains/environments. Simulation tests using a detailed SIMMECHANICS/ SIMULINK model of the employed MM are presented to illustrate and show the performance of the developed mechanisms.

Multimedia extensions based on Single-Instruction Multiple-Data (SIMD) units are widespread. They are used both in processors and accelerators (e.g., the Cell SPEs), since some time ago. SIMD units have usually big memory alignment constraints in order to meet power requirements and design simplicity. This increases the complexity of the code generated by the compiler, as in the general case, the compiler cannot be sure of the proper alignment of data. For that, the ISA provides either unaligned memory load and store instructions, or a special set of instructions to perform the realignments in software. In this paper, we propose a hardware realignment unit that takes advantage of the DMA transfers needed in accelerators with local memories. While the data is being transferred, it is realigned on the fly by our realignment unit, and stored with the proper alignment in the accelerator memory. The accelerator can then access the data with no special instructions. Finally, the data is realigned properly also when put back to main memory. Our experiments with four applications show that with our approach, the bandwidth of the DMA transfers is not penalized. And the performance of the synthetic benchmarks shows that aligned code is 1.5 to 2 times better with respect using unaligned code.

Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip multiprocessors have increased the memory bandwidth demands beyond what a single commodity memory device can provide. The immediate solution is to use more than one memory device, and interleave data across them so they can be used in parallel as if they were a single device of higher bandwidth. In this paper we showed that fine-grain memory interleaving on the evaluated many-core architectures with many DRAM channels was critical to achieve high memory bandwidth efficiency. Our results showed that performance can degrade up to 50% due to achievable bandwidths being far from the maximum installed.

Helical prospective ECG-gating (pECG) may reduce radiation dose while maintaining the advantages of helical image acquisition for coronary computed tomography angiography (CCTA). Aim of this study was to evaluate helical pECG-gating in CCTA in regards to radiation dose and image quality. 86 patients undergoing 64-multislice CCTA were enrolled. pECG-gating was performed in patients with regular heart rates (HR) < 65 bpm; with the gating window set at 70-85% of the cardiac cycle. All patients received oral and some received additional IV beta-blockers to achieve HR < 65 bpm. In patients with higher or irregular HR, or for functional evaluation, retrospective ECG-gating (rECG) was performed. The average X-ray dose was estimated from the dose length product. Each arterial segment (modified AHA/ACC 17-segment-model) was evaluated on a 4-point image quality scale (4 = excellent; 3 = good, mild artefact; 2 = acceptable, some artefact, 1 = uninterpretable). pECG-gating was applied in 57 patients, rECG-gating in 29 patients. There was no difference in age, gender, body mass index, scan length or tube output settings between both groups. HR in the pECG-group was 54.7 bpm (range, 43-64). The effective radiation dose was significantly lower for patients scanned with pECG-gating with mean 6.9 mSv +/- 1.9 (range, 2.9-10.7) compared to rECG with 16.9 mSv +/- 4.1 (P < 0.001), resulting in a mean dose reduction of 59.2%. For pECG-gating, out of 969 coronary segments, 99.3% were interpretable. Image quality was excellent in 90.2%, good in 7.8%, acceptable in 1.3% and non-interpretable in 0.7% (n = 7 segments). For patients with steady heart rates

Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware buffer. Fetching already decoded instructions avoids the need for decoding them again, improving processor performance. However, introducing such special--purpose storage in the processor design involves an important increase in the fetch architecture complexity. In this paper, we propose a novel decoding architecture that reduces the fetch engine implementation cost. Instead of using a special-purpose hardware buffer, our proposal stores frequently decoded instructions in the memory hierarchy. The address where the decoded instructions are stored is kept in the branch prediction mechanism, enabling it to guide our decoding architecture. This makes it possible for the processor front end to fetch already decoded instructions from the memory instead of the original nondecoded instructions. Our results show that using our decoding architecture, a state-of-the-art superscalar processor achieves competitive performance improvements, while requiring less chip area and energy consumption in the fetch architecture than a hardware code caching mechanism.

In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inter-frame dependencies have a limited spatial range. The previous results, however, investigate application scalability on an idealized multiprocessor. This work presents an implementation of the 3D-Wave strategy on a multicore architecture composed of NXP TriMedia TM3270 embedded processors. The results show that the parallel H.264 implementation scales very well, achieving a speedup of more than 54 on a 64-core processor. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the latencies of some frames might increase. To address these drawbacks, policies to reduce the number of frames in flight and the frame latency are also presented. The results show that our policies combat memory and latency issues with a negligible effect on the performance scalability.

Nowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is simultaneous multithreading (SMT). State-of-the-art high-performance processors like the IBM POWER5 and POWER6 corroborate this CMP+SMT trend. Within each SMT core any of the well-known SMT mechanisms may be applied to face SMT related challenges. Among them, probably the most important issue in an SMT execution pipeline concerns the instruction fetch (IFetch) Policy. The FLUSH IFetch Policy represents a choice for throughput-oriented scenarios. It handles L2 cache misses in order to avoid hardware resource monopolization by any given execution thread; involving an additional energy cost via instruction refetching. However, the new constraints imposed by the CMP+SMT scenario may affect well-known SMT mechanisms, like the FLUSH mechanism. In this paper we revisit the FLUSH mechanism and analyze its application in the emerging CMP+SMT scenario. The included analysis points out the new difficulties to be faced by the FLUSH mechanism in the emerging CMP+SMT scenario. Then we propose a novel IFetch Policy designed to cope with the CMP+SMT scenario: the MFLUSH. We also include a complete evaluation of the MFLUSH policy, both in terms of throughput and energy consumption. Our results indicate that the MFLUSH, specifically designed for the emerging CMP+SMT scenario, succeeds not only in overcoming the specific CMP+SMT constraints but also allowing a 20% energy consumption reduction without a significant system throughput loss.

General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies appear as a consequence for some programs. Reconfigurable hardware (cache hierarchy, branch predictor, execution units, bandwidth, etc.) has been proposed to overcome these inefficiencies by dynamically adapting the architecture to the application needs. However, nearly all the proposals use indirect measures or heuristics of performance to decide new configurations, what may lead to inefficiencies. In this paper we propose a runtime mechanism that allows to predict the throughput of an application on an architecture using a reconfigurable L2 cache. L2 cache size varies at a way granularity and we predict the performance of the same application on all other L2 cache sizes at the same time. We obtain for different L2 cache sizes an average error of 3.11%, a maximum error of 16.4% and standard deviation of 3.7%. No profiling or operating system participation is needed in this mechanism. We also give a hardware implementation that allows to reduce the hardware cost under 0.4% of the total L2 size and maintains high accuracy. This mechanism can be used to reduce power consumption in single threaded architectures and improve performance in multithreaded architectures that dynamically partition shared L2 caches.

The cell broadband engine (CBE) is designed to be a general purpose platform exposing an enormous arithmetic performance due to its eight SIMD-only synergistic processor elements (SPEs), capable of achieving 134.4 GFLOPS (16.8 GFLOPS * 8) at 2.1 GHz, and a 64-bit power processor element (PPE). Each SPE has a 256Kb non-coherent local memory, and communicates to other SPEs and main memory through its DMA controller. CBE main memory is connected to all the CBE processor elements (PPE and SPEs) through the element interconnect bus (EIB), which has a 134.4 GB/s bandwidth performance peak at half the processor speed. Therefore, CBE platform is suitable to be used by applications using MPI and streaming programming models with a potential high performance peak. In this paper we focus on the communication part of those applications, and measure the actual memory bandwidth that each of the CBE processor components can sustain. We have measured the sustained bandwidth between PPE and memory, SPE and memory, two individual SPEs to determine if this bandwidth depends on their physical location, pairs of SPEs to achieve maximum bandwidth in nearly-ideal conditions, and in a cycle of SPEs representing a streaming kind of computation. Our results on a real machine show that following some strict programming rules, individual SPE to SPE communication almost achieves the peak bandwidth when using the DMA controllers to transfer memory chunks of at least 1024 Bytes. In addition, SPE to memory bandwidth should be considered in streaming programming. For instance, implementing two data streams using 4 SPEs each can be more efficient than having a single data stream using the 8 SPEs

HD-VideoBench is a benchmark devoted to high definition (HD) digital video processing. It includes a set of video encoders and decoders (Codecs) for the MPEG-2, MPEG-4 and H.264 video standards. The applications were carefully selected taken into account the quality and portability of the code, the representativeness of the video application domain, the availability of high performance optimizations and the distribution under a free license. Additionally, HD-VideoBench defines a set of input sequences and configuration parameters of the video Codecs which are appropriate for the HD video domain.

One of the key deliverables of the EU HiPEAC FP6 Network of Excellence is a roadmap on high-performance embedded architecture and compilation --- the HiPEAC Roadmap for short. This paper is the result of the roadmapping process that took place within the HiPEAC community and beyond. It concisely describes the key research challenges ahead of us and it will be used to steer the HiPEAC research efforts. The roadmap details several of the key challenges that need to be tackled in the coming decade, in order to achieve scalable performance in multi-core systems, and in order to make them a practical mainstream technology for high-performance embedded systems. The HiPEAC roadmap is organized around 10 central themes: (i) single core architecture, (ii) multi-core architecture, (iii) interconnection networks, (iv) programming models and tools, (v) compilation, (vi) run-time systems, (vii) benchmarking, (viii) simulation and system modeling, (ix) reconfigurable computing, and (x) real-time systems. Per theme, a list of challenges is identified. In total 55 key challenges are listed in this roadmap. The list of challenges can serve as a valuable source of reference for researchers active in the field, it can help companies building their own R&D roadmap, and --- although not intended as a tutorial document --- it can even serve as an introduction to scientists and professionals interested in learning about high-performance embedded architecture and compilation.

H.264/AVC is a new international video coding standard that provides higher coding efficiency with respect to previous standards at the expense of a higher computational complexity. The complexity is even higher when H.264/AVC is used in applications with high bandwidth and high quality like high definition (HD) video decoding. In this paper, we analyze the computational requirements of H.264 decoder with a special emphasis in HD video and we compare it with previous standards and lower resolutions. The analysis was done with a SIMD optimized decoder using hardware performance monitoring. The main objective is to identify the application bottlenecks and to suggest the necessary support in the architecture for processing HD video efficiently. We have found that H.264/AVC decoding of HD video perform many more operations per frame than MPEG-4 and MPEG-2, has new kernels with more demanding memory access patterns and has a lot data dependent branches that are difficult to predict. In order to improve the H.264/AVC decoding process at HD it is necessary to explore a better support in media instructions, specialized prefetching techniques and possibly, the use of some kind of multiprocessor architecture.

SIMD extensions are the most common technique used in current processors for multimedia computing. In order to obtain more performance for emerging applications SIMD extensions need to be scaled. In this paper we perform a scalability analysis of SIMD extensions for multimedia applications. Scaling a 1-dimensional extension, like Intel MMX, was compared to scaling a 2-dimensional (matrix) extension. Evaluations have demonstrated that the 2-d architecture is able to use more parallel hardware than the 1-d extension. Speed-ups over a 2-way superscalar processor with MMX-like extension go up to 4X for kernels and up to 3.3X for complete applications and the matrix architecture can deliver, in some cases, more performance with simpler processor configurations. The experiments also show that the scaled matrix architecture is reaching the limits of the DLP available in the internal loops of common multimedia kernels.

The prophet/critic hybrid conditional branch predictor has two component predictors. The prophet uses a branch's history to predict its direction. We call this prediction and the ones for branches following it the branch future. The critic uses the branch's history and future to critique the prophet's prediction. The hybrid combines the prophet's prediction with the critique, either agrees or disagree, forming the branch's overall prediction. Results shows these hybrids can reduce mispredicts by 39 percent and improve processor performance by 7.8 percent.

Since embedded systems require ever more compute power, SMT processors are viable candidates for future high performance embedded processors. However, SMTs exhibit unpredictable performance due to uncontrolled interaction of threads. Hence, the SMT hardware needs to be adapted in order to meet (soft) real time constraints. We show by a simple policy that the OS can exercise control over the execution of a thread which is required for real time constraints.

Fetch engine performance is seriously limited by the branch prediction table access latency. This fact has lead to the development of hardware mechanisms, like prediction overriding, aimed to tolerate this latency. However, prediction overriding requires additional support and recovery mechanisms, which increases the fetch architecture complexity. In this paper, we show that this increase in complexity can be avoided if the interaction between the fetch architecture and software code optimizations is taken into account. We use aggressive procedure inlining to generate long streams of instructions that are used by the fetch engine as the basic prediction unit. We call instruction stream to a sequence of instructions from the target of a taken branch to the next taken branch. These instruction streams are long enough to feed the execution engine with instructions during multiple cycles, while a new stream prediction is being generated, and thus hiding the prediction table access latency. Our results show that the length of instruction streams compensates the increase in the instruction cache miss rate caused by inlining. We show that, using procedure inlining, the need for a prediction overriding mechanism is avoided, reducing the fetch engine complexity.