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We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2 process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.

This paper describes a cryogenic multi-chip module (MCM) probe for testing of a superconducting hybrid digital signal processor (DSP) capable of 24 giga multiply accumulate operations per second. The probe has 39 data channels with 4 GHz bandwidth, a 30 GHz high speed clock input line, and 48 biasing lines. The MCM interface board features 164 spring finger contacts for a 30 times 30 mm2 MCM. The probe has low heatload (0.23 W) and provides good magnetic shielding with residual field equal to 250Phi0 over a 5 times 5 mm2 area. The measured time skew between 20 of the 1200 mm data coaxial lines is about 70 ps. The probe allows synchronous data word transmission at 2 Gbps.

We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2 process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm2 process.

The balanced comparator is an essential part of RSFQ-based readout for superconducting qubits. In this paper we report measurements of the sensitivity of the balanced comparator fabricated in a specialized 30 A/cm2 process with 3.6 muA critical currents and measured at 30-500 mK. At sampling frequency of 3.5 GHz the measured gray zone is DeltaI = 104 nA. Due to electron overheating in the shunt resistors the effective noise temperature is 140 mK. The gray zone has a strong dependence on sampling frequency above 5 GHz due to over-clocking. Related measurements have been reported where cooling fins and reduced critical current density of 10 A/cm2 were used, and a quantum limited gray zone of 40 nA was achieved. This makes single shot readout possible for the phase, RF-SQUID and persistent current qubits. The readout speed is 30-50 ps, which is quite favorable for error correction schemes.

This paper presents results of optimization of Multi-Chip-Module (MCM) contact pads and driver circuitry for gigabit chip-to-chip communication. Optimization has been done using 3D Electromagnetic (EM) simulations of flip-chip contacts and time domain simulations of drivers and receivers. A single optimized flip-chip contact has signal refection of less than -20 dB for up to 503 GHz bandwidth. The MCM data link with optimized SFQ driver, receivers and two MCM contact has operational margins on global bias current of +-30% at 30 Gbit/s speed and can operate at maximum 113 Gbit/s of operational speed. High bandwidth transmission requires realization of an advanced flip-chip process with small dimension of contact pads (less 30 micro meter) and small hight of bumps in the order of 2 micro meter. Current processes with about 7 micro meter hight of the bumps requires application of Double Flux Quantum (DFQ) driver. The data link with DFQ driver was also simulated. It has operational margins on global bias current of +-30% at 30 Gbit/s, however the maximum speed of operation is 61 Gbit/s. Several test structures have been designed for measurements signal re°ection, bit error rate (BER) and operational margins of the data link.

Rapid single-flux-quantum (RSFQ) technology has been proposed as control electronics for superconducting quantum bits because of the material and working temperature compatibility. In this work, we consider practical aspects of RSFQ circuit design for low noise low power operation. At the working temperature of 20 mK and operational frequency of 2 GHz, dissipated power per junction is reduced to 25 pW by using 6 νA critical current junctions available at the Hypres and VTT low Jc fabrication process. To limit phonon temperature to 30 mK, a maximum of 40 junctions can be placed on a 5 mm × 5 mm chip. Electron temperature in resistive shunts of Josephson junctions is minimized by use of cooling fins, giving minimum electron temperatures of about 150 mK for the Hypres process and 70 mK for the VTT process.

We have designed and experimentally verified a test bench for high frequency testing of Rapid Single Flux Quantum (RSFQ) circuits. This test bench uses an external tuneable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift-register. The clock pattern is consequently shifted out at high speed and splitted to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed readout electronics. The test bench consists of 158 Josephson junctions and occupied area is 3300 * 660 (mikro meter)^2. It was experimentally verified up to 33 GHz with +- 21.7 % margins on the global bias supply current.

In this paper, issues related to the optimization of superconducting passive interconnects are discussed. Results of the microwave optimization of bends, via connections and crossings of superconducting microstrip lines (SMSLs) are reported. The optimum design of the SMSL cross gives more than 95% of transmission and can be well used in a two-bus cross design with up to 14 signal wires. The results have been confirmed by time-domain simulations and measurements.

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 parallel multipliers, 4 /spl times/ 5, 20 /spl times/ 5 and 4 /spl times/ 15 parallel shift registers have been designed and experimentally tested.

Two effects of the bias supply line on the performance of RSFQ circuits have been studied: inductive coupling between the bias supply line and circuit inductances; effect of the mirrored current in the ground plane. The following results of the study are presented: 3D calculations and experimental measurements of inductive coupling between parallel and perpendicular microstrips in presence of one and two ground planes; calculated margins dependence on the external magnetic field in RSFQ cell. Bias current density extraction method has been developed and implemented in RSFQ circuit design flow.

A set of standard rapid-single-flux-quantum logic cells has been established in order to build blocks for complex high-speed superconducting digital applications. Special emphasis has been put on the implementation with Nb and NbN technologies as well as with high-Tc superconductors. The influence of the different technological parameters on the projected performance of some basic cells is presented along with a comparative study of their margins of operation. In particular, the performance of a D-flip-flop has been studied as a function of frequency of operation for the different technologies.

We have developed a low temperature transmission spectrometer operating in a wide range of frequencies from 100 GHz to 1.7 THz. The spectrometer has utilized the unique properties of high-Tc superconducting Josephson junctions and the wideband response of sensitive Cold-Electron Bolometers (CEB). The voltage response of the CEB integrated with log-periodic and double-dipole antennas, has been measured using an oscillator consisting of high-Tc Josephson junction integrated on a separate substrate with a log-periodic antenna. Superconducting Josephson junctions with high characteristic voltages (IcRn larger than 4 mV at 4.2 K) are fabricated by depositing YBa2Cu3O7-x on miscut sapphire bi-crystal substrates, where the tilting axis is along the grain boundary. The cold electron bolometer having a superconductor-insulator-normal metal-insulator- superconductor (SINIS) structure was 200 nm wide, 10 µm long, and terminating tunnel junctions were 200x300 nm² area. The response of the bolometer with a double dipole antenna has resonance shape with maximum corresponding to the designed central frequency of 300 GHz. A voltage response of the bolometer up to 4·10 8 V/W corresponds to a noise equivalent power of the bolometer of 1.2·10 -17 W/Hz 1/2 . Our measurements demonstrate that the Josephson junction is overheated by the transport current up to 3 K at 1 mV bias when it is placed on a millikelvin stage. A high-Tc Josephson junction operated at temperatures below 2 K has the advantage of a high IcRn product that enhances the oscillation frequency to above 2 THz. The

For sensitive wideband spectroscopy at TeraHertz frequencies one needs a wide-range electrically tunable THz source and a sensitive detector. In this paper a superconducting normal metal cold electron bolometer (CEB) was used as a broadband sensor. Bolometers were integrated with broadband log-periodic antenna designed for 0.2-2 THz frequency range and double-dipole antennas designed for 300 and 600 GHz central frequency. A Josephson junction was used as a wide band electrically tuned terahertz cryogenic oscillator. Bicrystal YBaCuO Josephson junctions demonstrated a characteristic voltage IcRn of over 4 mV that corresponds to characteristic frequency about 2 THz. The bolometer chip is attached to a Si substrate lens at 260 mK and the oscillator chip is attached to the sapphire substrate lens at 1.8 K, with lenses facing each other at the distance of few centimeters. High signal was measured in the whole frequency range up to 1.7 THz by simple changing the bias voltage of Josephson junction from zero to 3.5 mV. A voltage response of the bolometer up to 4*108 V/W corresponds to an amplifier-limited technical noise equivalent power of the bolometer NEP=1.25*10-17 W/Hz1/2. Combining a Terahertz band Josephson junction, a high-sensitive hot electron bolometer, and a sample under test in between, makes it possible to develop a cryogenic compact Terahertz-band transmission spectrometer with a resolution below 1 GHz corresponding to the linewidth of Josephson oscillations. For frequencies below 600 GHz a conventional Nb shunted SIS junction can be used as Josephson oscillator.