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In this study, new kinds of hydrogen-bonded (H-bonded) chiral molecular switches (CMS) composed of azobenzene moieties as photo-responsive parts and H-bonded complexes as thermo-responsive parts were developed. Photo- and thermally-reversible switching behavior of cholesteric liquid crystals (Ch-LCs) based on the H-bonded CMS was investigated in detail. The results demonstrate that H-bonded CMS undergo a trans–cis photoisomerization under UV light, which results in the decrease of helical twisting power (HTP). Meanwhile, the modulation of the intermolecular forces between proton donors and acceptors with temperature has a positive influence on the change in HTP. Reversible blue, green, and red reflections of the self-organized helical superstructure could be achieved under UV/Vis light as well as with temperature change. According to the geometry optimization based on Gaussian 03 calculations at the B3LYP/6-31G(d) level, the molecular aspect ratio could be considered to be one of the important factors influencing the HTP of H-bonded CMS. This dynamic tuning of the self-organized helical superstructure based on dual and selective molecular mechanism opens up a way to achieve new kinds of LC photonic materials.

A novel class of hydrogen-bonded chiral azobenzene switches was developed to induce an optically tunable liquid crystal blue phases (LC-BPs), which leads to the stabilization of the LC-BPs for a wider temperature range and is capable of a reversible phototuning of the reflection color of BP I over the visible wavelength region.

Phase noise causes a common phase error (CPE) and inter-carrier interferences (ICI) in OFDM systems. In this paper, a novel CPE and ICI cancellation method is proposed. Comparing with compensating only the CPE, the proposed method shows significant BER improvements. These improvements are demonstrated using simulation results of an ultra-wideband system employing this CPE and ICI cancellation technique. The cost of implementation is low.

A 300-MHz quadrature direct digital frequency synthesizer/complex mixer (QDDSM) chip is presented. With a 32-bit input frequency control word, the tuning resolution is 0.07 Hz at the operating frequency of 300 MHz. The 12-bit I and Q inputs and 13-bit I and Q outputs offer a spurious-free dynamic range of 90.3 dB. The tuning latency is 13 clock cycles, which corresponds to 43 ns at 300 MHz. The tuning bandwidth (half the operating frequency) is 150 MHz. The IC is realized in 0.25-/spl mu/m TSMC CMOS technology with 4180 standard library cells and occupies a core area of 0.36 mm/sup 2/. At 300 MHz, the power dissipation is less than 400 mW. A key feature of the design is the creation of conditionally negating multipliers.

A reconfigurable angle rotator architecture is proposed and incorporated into an energy-efficient reconfigurable FFT/IFFT processor IC as its major computation component, endowing the FFT/IFFT processor with a significant scalable power dissipation feature with varying FFT size. The reconfigurability of the angle rotator is realized by dynamically allocating computation resources, which are subrotation stages in cascade. This approach tends to minimize the size of the lookup table while maintaining computation accuracy, and tends to minimize the area and power consumption while improving the overall performance.

With a 32-bit frequency-control-word and two 15-bit (I and Q) data inputs, while employing less hardware than a conventional 2-multiplier/DDFS approach, this interleaved IC provides a quadrature DDFS (nearly for free!) with 100 dB spurious-free dynamic range and produces a 16-bit modulated sinusoidal output. Power dissipation is 0.5 W at an 830 MHz clock-rate with a 2.5 V supply.

A 400-MHz digital rectangular-to-polar coordinate converter has been implemented in 0.25-/spl mu/m CMOS. The inputs to the chip are 14-bit in-phase and quadrature channels, and the outputs are 15-bit magnitude and phase channels. The phase and magnitude calculations have a maximum error of 0.00024 and 0.03, respectively. At a maximum frequency of 406 MHz, the circuit dissipates 470 mW of power at 2.5 V.

We present an architecture for high performance sine/cosine generation and angle rotation. Unlike CORDIC-type methods, which implement rotation using a sequence of subrotation stages, each realized, with a butterfly structure, the proposed approach implements the rotation with just two stages. We perform approximately the same number of arithmetic operations in our architecture as in CORDIC-type processors, but our architecture consolidates the operations into small array-multipliers, which can yield a smaller and faster circuit using well-known efficient multiplier implementation techniques (such as Booth encoding).

All-digital approaches for the adjustment of timing offset in digital modems have attracted increasing attention. We recently announced a novel interpolation method which, instead of approximating the continuous-time signal with a conventional polynomial and computing the synchronized samples using a Farrow structure, uses a trigonometric polynomial. Simulation results indicate that improved performance, reduced computational delay and, in most cases, simplified hardware can be achieved. To recover a synchronized sample from existing samples, given a timing offset, we show here that we can optimize this method such that the interpolation error in the recovered sample is minimized for that specific timing offset value. Using this optimization technique, the overall interpolation error is reduced. As for the implementation, the optimal interpolator does not require additional hardware as compared to our original method.