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The self-assembly (SA) of diblock copolymers (DBCs) based on phase separation into different morphologies of small and high-density features is widely investigated as a patterning and nanofabrication technique. The integration of conventional top-down approaches with the bottom-up SA of DBCs enables the possibility to address the gap in nanostructured lateral length standards for nanometrology, consequently supporting miniaturization processes in device fabrication. On this topic, we studied the pattern characteristic dimensions (i.e., center-to-center distance L0 and diameter D) of a cylinder-forming polystyrene-b-poly( methyl methacrylate) PS-b-PMMA (54 kg mol–1, styrene fraction 70%) DBC when confined within periodic SiO2 trenches of different widths (W, ranging between 75 and 600 nm) and fixed length (l, 5.7 μm). The characteristic dimensions of the PMMA cylinder structure in the confined configurations were compared with those obtained on a flat surface (L0 = 27.8 ± 0.5 nm, D = 13.0 ± 1.0 nm). The an...

A metal/oxide/high-kappa dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO2 as tunnel oxide, Al-HfO2 as charge trapping layer, SiO2 as blocking oxide and TaN metal gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900 degrees C in N-2, as required for standard complementary metal-oxide-semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of +/- 20 V to +/- 12 V. When compared to a benchmark structure including thin Si3N4 as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (kappa) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-kappa based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices.

Resistance switching random access non-volatile memories (ReRAM) could represent the leading alternative to floating gate technology for post 32 nm technology nodes. Among the currently investigated materials for ReRAM, transition metal binary oxides, such as NiO, CuxO, ZrOx, TiO2, MgO, and Nb2O5 are receiving increasing interest as they offer high potential scalability, low-energy switching, thermal stability, and easy integration in CMOS fabrication. In this work we investigate the resistive switching properties of NiO and Nb2O5 films grown by electron beam and atomic layer deposition (ALD) as a function of growth technique and electrode materials. The polycrystalline NiO and amorphous Nb2O5 films are initially in the high resistance state and exhibit reproducible unipolar switching after an appropriate forming stage. Beside noble metal electrodes, particular focus is on n(+)-Si, W, and TiN materials which are compatible with CMOS device fabrication process. (C) 2008 Elsevier B.V. All rights reserved.

Ge1-xSbxTey thin films, grown by metalorganic and hot-wire liquid injection chemical vapor deposition in different crystalline phases, are investigated to determine resistivity, carrier density, and carrier mobility in the 4.2-300 K temperature range. It is found that all these chalcogenides exhibit p-type conduction, high carrier density (>2 . 10(20) cm(-3)), and no carrier freeze-out, regardless of composition. Low-temperature mobility data show that both chemical composition and growth technique affect the defect density and, in turn, the carrier scattering mechanisms. In this regard, charge carrier mobility is analyzed according to semi-empirical scattering models and an interpretation is provided.