1. A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium
- Author
-
Leibo Liu, Bohan Yang, Wenping Zhu, Hanning Wang, Cankun Zhao, Min Zhu, Shouyi Yin, Neng Zhang, Zhengdong Li, and Shaojun Wei
- Subjects
Hardware architecture ,Computer engineering. Computer hardware ,Materials science ,business.industry ,CRYSTALS-Dilithium ,Information technology ,T58.5-58.64 ,post-quantum cryptography ,Dilithium ,TK7885-7895 ,chemistry.chemical_compound ,chemistry ,digital signature ,module learning with errors ,business ,Computer hardware ,FPGA - Abstract
The lattice-based CRYSTALS-Dilithium scheme is one of the three thirdround digital signature finalists in the National Institute of Standards and Technology Post-Quantum Cryptography Standardization Process. Due to the complex calculations and highly individualized functions in Dilithium, its hardware implementations face the problems of large area requirements and low efficiency. This paper proposes several optimization methods to achieve a compact and high-performance hardware architecture for round 3 Dilithium. Specifically, a segmented pipelined processing method is proposed to reduce both the storage requirements and the processing time. Moreover, several optimized modules are designed to improve the efficiency of the proposed architecture, including a pipelined number theoretic transform module, a SampleInBall module, a Decompose module, and three modular reduction modules. Compared with state-of-the-art designs for Dilithium on similar platforms, our implementation requires 1.4×/1.4×/3.0×/4.5× fewer LUTs/FFs/BRAMs/DSPs, respectively, and 4.4×/1.7×/1.4× less time for key generation, signature generation, and signature verification, respectively, for NIST security level 5.
- Published
- 2021