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One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. Because it prevents inputs arriving at a stage, which is stalled, it can also be used in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of 8%–12% with a target throughput of 0.9 instructions per cycle, and 15%–18% when the target is 0.8.

Level-sensitive latches are widely used in high-performance custom designs while edge-triggered flip-flops are predominantly used in application-specific integrated circuits. We consider a latch as a basis for storage and address each step of high-level synthesis (HLS), including scheduling, allocation, and control synthesis. While the use of latches provides an opportunity to reduce the latency during the scheduling, the register allocation has to take extra conflicts caused by latch into account, and the control synthesis has to be tailored to support the latch-based data-path. Optimization potentials specific to this HLS are identified and solutions are proposed. Specifically, the register allocation can be improved by refining the operation schedule in a way to reduce the number of edges in a register conflict graph; the latency can be reduced by adjusting the clock duty cycle in a way to generate a tighter schedule. All the steps of HLS and optimization procedures were integrated into a framework called HLS-l. It was tested on benchmark designs implemented in 1.1-V, 45 nm complementary metal-oxide-semiconductor technology. Compared to the conventional HLS, HLS-l was able to reduce the latency by 18.2% on average with 9.2% less area and 16.0% less power consumption. The application of HLS-l to an industrial example is demonstrated through the design of a module extracted from H.264/advanced video coding.

Imposing regularity presents a fundamental limitation to any structured ASIC, or more generally any programmable logic device. It has been recently shown that irregularity can be introduced in structured ASIC, in particular in programmable logic elements of structured ASIC, through a special photolithography process, and the degree of irregularity can be customized for each particular design by manufacturing a few extra masks. We experiment how irregularity can be introduced to routing architecture of structured ASIC. When a whole routing area is made of an array of two routing architectures, the area is reduced by 8% to 16% (compared to standard structured ASIC) due to less white space, which is made possible by improved routability; the total wirelength is reduced by 6% to 14%. The new routing architectures and routing algorithm specific to the architectures are presented.

Conventional structured ASIC still suffers from large delay and area due to the use of homogeneous array of tiles. We propose a new lithography method called selectively patterned masks (SPM), which enables more than one type of tiles to be used in structured ASIC. This structured ASIC using mixture of different tiles relaxes regularity. To assess SPM concept, A new structured ASIC is proposed; tile and routing architecture, and routing algorithm are all addressed. Experiment results using 45-nm technology show that proposed concept can push the limit of structured ASIC closer to traditional ASIC.

Active leakage current is much larger (~ 10x) than standby leakage current, and takes a large proportion (30% to 40%) of active power consumption. Active mode power gating (AMPG) has been proposed to extend the application of basic power gating to reducing active leakage; it relies on clock-gating signals to cut the power off a part of combinational gates. The problem to select those gates while integrity of circuit behavior remains intact has not been solved yet. We identify three constraints to solve this problem, namely functional, timing, and current constraints. The problem of synthesizing AMPG circuits is then laid out, and synthesis algorithm is proposed; a group of gates that can be power-gated by each clock-gating signal and the size of footer that is attached to the group constitute a synthesis output. The layout methodology for standard cell designs is proposed to assess AMPG circuits in area and wirelength. Experiments in 1.1 V, 45-nm technology demonstrate that active leakage is reduced by 16% on average compared to clock-gated circuits.

Reducing the power consumption of memory elements is known to be the most influential in minimizing total power consumption, since designs tend to use more memories these days. In this paper, we address a problem of high-level synthesis with the objective of minimizing power consumption of storage using dual-V dd . Specifically, we propose a complete design framework that starts from dual-V dd scheduling, dual-V dd allocation, and controller synthesis down to the final layout. Its main feature is dual-V dd register allocation, which exploits timing slacks left in the data-path after operation scheduling. In experiments on benchmark designs implemented in 1.08 V (with V ddl of 0.8 V), 65-nm CMOS technology, both switching and leakage power were reduced by 20% on average, respectively, compared to data-path with dual-V dd applied to functional units alone. Detailed analysis of slack histogram, area, wirelength, and congestion were performed to assess feasibility of the design framework.