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Roughness has always been a key detractor of the optical losses within the silicon photonics devices. With scaling at 300mm wafer, there is an introduction of new tools such immersion lithography scanner, OPC technique that can help to drive furthermore the optical losses reduction. This study will detail the work done on characterizing multiple steps of the process (Lithography, Etch, Annealing) and using roughness tools such LER (Line Edge Roughness), LWR (Line Width Roughness) and finally PSD (Power Spectral Density) to understand the main detractor of the optical losses at each step. These data will be extracted using SEM imaging from VeritySEM 6i.

International audience; It has previously been reported that epitaxial growth of ZnO can be obtained at low temperatures by atomic layer deposition (ALD) onto a GaN (0001-Ga) surface, corresponding to a ~2.3% compressive lattice mismatch of the deposited ZnO. The question addressed here is the atomic ordering of deposited ZnO as a function of the lattice mismatch between ZnO and several single-crystal seeding surfaces. We have deposited ZnO using ALD onto either the (111) cubic or (0001) hexagonal surfaces of a set of available single-crystal substrates (GaAs, InP, GaN, SiC), for which the lattice mismatch varies over a wide range of values, positive and negative. It is found that deposition onto surfaces with very high extensive lattice mismatch (GaAs, InP) leads to polycrystalline ZnO, similar to the configuration obtained on an amorphous SiO2 surface. In contrast, ZnO ALD deposition onto both 2H-GaN (0001-Ga) and 4H-SiC (0001-Si) surfaces with lower and compressive mismatch leads to epitaxial ordering over the whole substrate temperature range of 180–250 ◦C