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This paper presents a PV system featuring two grid modes; on and standalone (off) mode. The main purpose of this work is verifying the effectiveness and feasibility of the power flow management strategy of the proposed system to fulfill the connected load demand with best utilization of considered sources, analyze the PV system performance under different grid modes. In case of normal grid conditions (mode ON), the PV system is connected to a three-phase grid and AC load. It supplies the load and grid in case of excess of PV power, and shares the peak load demands between grid and PV system. In case of grid faults, PV switches to off-grid mode, which it supplies the connected load and battery bank. The latter can store excess PV power or supplies the load in case of low or zero irradiances. The considered system tested using MATLAB/ Simulink.

This paper studies the suitability of System-on-Chip (SoC) devices to perform Embedded Real-Time Simulators (eRTS) of electrical systems. These new devices combine powerful ARM processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for controlling, monitoring and emulating a complete electrical system. There are two main categories of elements with their own respective characteristics and constraints: electromechanical/electromagnetic systems, and switching elements. Accordingly, the proposed investigation will focus on a Doubly-Fed Induction Generator (DFIG) on one hand, and on a Modular Multi-level Converter (MMC) on the other hand. In addition to Real-Time (RT) simulation results, SoC time/resources evaluations will be presented for different implementation strategies: full-software, full-hardware based on High-Level Synthesis (HLS) tools, and using 64/32-bit floating- and fixed-point formats. The validity of the MMC implementation will be tested experimentally.

Model-predictive control (MPC) is an advanced model-based control technique. It allows flexible control schemes with fast time responses. However, like most optimization-based control strategies, MPCs are usually computationally intensive and suffer from a lack of robustness toward parametric variations. The computational burden of these controllers is nowadays being relieved thanks to the progress of digital devices; however, the robustness is still a major issue that prevents the use of MPC controllers in some applications. Systems presenting slow and fast dynamics at the same time are usually controlled by cascaded control loops. MPC techniques are restricted to the control of inner loops, while outer loops use more robust control techniques. The aim of this paper is to provide MPC techniques for both the inner and outer loops of an active front-end rectifier. A first dual-MPC cascaded control shows the drawbacks of usual MPC techniques for outer loops. It is thereafter modified to achieve a robust cascaded dual-MPC that eliminates the variable resistive load parameter from the system dynamical model and formulates a new prediction model containing only known parameters and measurable quantities. Finally, a third method based on the previous one is also presented in order to reduce switching losses. Experimental results for the three methods are presented and compared with double precision offline software simulation results to validate the feasibility of the proposed techniques.

Comunicació presentada a IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society (October 21-23, 2018 Washington D.C., USA.) System-on-Chip (SoC) devices combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for Hardware-in-the-Loop (HIL) simulation. One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which need extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ and SystemC. This paper evaluates SoC devices to implement a Modular Multi-Level Converter (MMC) model using HLS tools for being implemented in the FPGA fabric in order to perform HIL verification of control algorithms in a single low-cost device.

System-on-Chip (SoC) devices combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for controlling and monitoring a complete system. These characteristics make them very suitable to implement Embedded Real-Time Simulators (ERTS), which provide interesting and powerful functionalities (such as observers, parameter estimation, diagnostic, health monitoring, etc.) but increasing significantly the complexity of the controller. The main drawback of these devices is that control engineers are not particularly familiarized with FPGA programming, which need extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ and SystemC. This paper evaluates SoC devices to implement several versions of a Modular Multi-Level Converter (MMC) using HLS tools. An improved simplified model of the converter which includes the modulation, the voltage balancing algorithm, and the circulating current control keeping record of every sub-module (SM) capacitor voltage. The MMC model will be evaluated changing the number of SM from 6 to 700 per phase, and using three different formats for the variables and parameters: 64-bit floating-point, 32-bit floating-point, and 32-bit fixed-point variables. The different versions of the ERTS will be compared in terms of computational power, area utilization and precision.

Grid connected power converters are widely used to interface between grid – on one side- and loads or renewable energy sources – on the other side. This work presents an indirect sliding mode power control (ISMPC) for three phase grid connected power converter. This control is characterised by improved robustness with regard to external disturbances and parameters changes, while insuring at the same time low current total harmonic distortion factor. The development and implementation of the ISMPC algorithm on low cost Microsemi SmartFusion digital solution is also described. This digital solution includes in the same chip a Field Programmable Gate Array (FPGA) fabric and a Cortex-M3 processor associated to large number of peripheral cores. The developed ISMPC is compared with standard and commonly used controls for grid connected converters to show its interest and advantages. Moreover, an overview of the experimental set-up, the description of the algorithm modular partitioning between FPGA and processor, the resources optimisation as well as the execution time reduction are presented. Selected experimental results corresponding to different operation steps are presented to illustrate performances and effectiveness of the proposed ISMPC algorithm.

In this paper, a novel rotor position estimator for an interior permanent magnet synchronous motor is presented and evaluated. The proposed estimator lies on one of the most popular methods in the field of artificial intelligence: Machine learning-based neural networks algorithm. The main interest is to introduce a cost-efficient position estimator that is comparable to classic methods in terms of functional performances. The estimator model is built by learning from a dataset that associates phase currents and voltages to the rotor position. Learning signals are generated using a simulation model. This is primarily intended to save the resources invested in testbench trials. In this work, offline training steps and results are described and commented. The efficiency of the proposed position estimator is first verified by functional simulations. Second, real-time experiments are conducted on an actual scale testbench. The NN-based estimator covers a wide speed range and is implemented in the context of IPMSM-based EV traction drives. More broadly, these findings can also be applicable to the ac-based electric drives for the position estimation purpose.

DC link filter capacitors used in electric drives for automotive applications are most of the time aluminum electrolytic capacitors. However their high sensitivity to temperature results in very we...

International audience; This paper aims to provide Hardware/Software (Hw/Sw) codesign guidelines for system-on-chip field-programmable gate array-based sensorless ac drive applications. Among these guidelines, an efficient Hw/Sw partitioning procedure is presented. This Hw/Sw partitioning is performed taking into account both the control requirements (bandwidth and stability margin) and the architectural constraints (e.g., available area, memory, and hardware multipliers). A nondominated sorting genetic algorithm (NSGA-II) is used to solve the corresponding multi-objective optimization problem. The proposed Hw/Sw partitioning approach is then validated on a sensorless control algorithm for a synchronous motor based on an extended Kalman filter. Among the nondominated implementation solutions supplied by the NSGA-II, those that are considered as the most interesting are synthesized. Their time/area performances after synthesis are compared with success to their predictions. In addition, one of these optimal solutions is also tested on an experimental setup.

Most of automotive applications rely on Permanent Magnet Synchronous Machines (PMSMs) thanks to the afforded high efficiency and reduced cost and size. However, this trend is subject to severe safety requirements, particulary related to the reliability of the mechanical position sensor. In this context, the present paper deals with PMSM sensorless control, aimed at providing the position information redundancy. Yet, some side effects, as saturation and cross-coupling, may compromise the estimation quality. To achieve a deeper insight into the impact of these phenomena, authors highlight the way that sensorless estimation accuracy is predicted from the rotor geometry anisotropy. The objective is two-fold: 1) Provide a detailed approach for the characterization of the PMSM magnetic model under different load conditions, 2) Deduce the machine saliency behaviour and the induced estimation error due to saturation effects. To do so, an accurate flux linkage model is required. This model should allow to evaluate the arising cross-saturation terms. Experimental results are presented, referring to two test traction motors dedicated to the electric vehicle application.

New System-on-Chip (SoC) devices, which include powerful general purpose processors and FPGA in the same chip are particularly suitable for Real-Time (RT) simulation of electromechanical systems. This paper introduces a systematic analysis of the capabilities of one of these devices for RT electromagnetic simulation. Considering all the capabilities of these platforms, it is not straightforward to use them efficiently and port existing developments due to the SoC relative complexity and variety of programming models. In this paper, authors evaluate some of the benefits of moving to such platforms through the implementation of an example application on the Xilinx Zynq-7000 SoC. Simulation results concerning execution time, resources usage and precision of the calculations are presented, compared and validated using MATLAB/Simulink.

The paper deals with the sensorless control of salient-pole Interior-Permanent-Magnet-Synchronous-Machines (IPMSMs) adressed to electric vehicle applications, using a high frequency voltage injection technique. This technique is effective at zero and low motor speed, and takes advantage of the peculiarity of the rotor geometry. Indeed, the expected estimation performances heavily depend on the rotor saliency, so, on the geometry of the IPMSM rotor. The main focus of this work is first to experiment the magnetic saturation effect on the machine saliency for different operating conditions and consequently identify the feasible sensorless control region when taking into account the chosen current control strategy. Then, it is intended to evaluate the impact of saturation induced cross-coupling terms on the position estimation accuracy. This analysis is supported by experimental evidence obtained using a salient-pole interior PM synchronous machine, however, the findings may also be applicable to other AC salient machines.

This article presents the benefits of using field-programmable gate array (FPGA)-based controllers for power electronics and drive applications. For this purpose, an algorithm perspective is first proposed, where it is stated that, depending on the intrinsic parallelism properties as well as level of complexity, it makes sense to implement each control algorithm on a specific hardware and/or software architecture to get the best performances in terms of execution time or the best ratio performance versus cost. Then, an application perspective is proposed where the constraints specifically linked to the control of power converters are discussed.

This paper proposes a current Model Predictive continuous Real-Time Simulator (RTS) on the Zynq-7000 All Programmable (AP) System-on-Chip (SoC). This device is a new integrating an FPGA fabric along with a powerful processor. The RLE load dynamical model is implemented in the FPGA fabric of the Zynq-7000 and is run at very high frequencies (50 MHz) to the hardware and software capabilities of the chosen Zynq-7000 AP SoC device. Real-time simulation results are presented and MATLAB.

This paper analyses the capacity of a new FPGA-based System-on-Chip (SoC) platform for the control of electrical systems. These new SoC platforms integrate both an FPGA fabric and a powerful processor. Among these platforms the Xilinx Zynq-7000 All Programmable (AP) System on-Chip is evaluated. The chosen algorithmic benchmark consists on a realtime simulation of a Voltage Source Rectifier (VSR) connected to the grid and supplying a resistive load. This VSR is controlled via a Model Predictive Control technique. The VSR dynamical model is implemented in the FPGA fabric of the Zynq-7000 while the predictive controller is implemented in its processing part. Both software and hardware parts of the benchmark are challenging. The model predictive control technique is computationally intensive. Moreover, the VSR model should approximate a quasi continuous-time behavior which implies that its dynamical model has to be executed at very high frequencies (10 MHz). Realtime simulation results are presented and compared with double precision off-line software simulation results.

The aim of this paper is to quantify the interest of using hardware field-programmable gate arrays (FPGAs) to implement complex control algorithms. As a benchmark, authors have chosen a sensorless speed controller for a synchronous motor. The estimation of the rotor position and speed is achieved using an extended Kalman filter (EKF), eliminating the need of their corresponding mechanical sensors. Due to the EKF complexity, such sensorless controller is systematically implemented in a software digital signal processor (DSP) device. The execution time is frequently evaluated to several tens or hundreds of microseconds. The motivation here is to prove that, when exploiting the treatment fastness of FPGAs (less than 6 μs ), it is possible to enhance the control bandwidth. To reach this objective, a comparison between the developed FPGA-based sensorless speed controller and its DSP-based counterpart is made. The same sensorless controller (with the same complexity) has been implemented in both cases. To prop up this comparison, simulation, hardware-in-the-loop, and experimental tests are presented.

International audience; The recent field programmable gate array (FPGA) system on chip devices offer a new degree of design freedom. Indeed, these digital components allow the combination of software treatment (by the on-chip processor cores) and hardware treatment (hardware architecture made by the interconnection of the FPGA logic cells). In the field of industrial control applications, this digital technology is appropriate to reach an optimum between the control performances, the controller algorithm complexity and the design flexibility. On the other hand, a co-design methodology is necessary to make an efficient partitioning of the control algorithm so as to define modules to be software-made and modules to be hardware-made. To this aim, this paper deals with a co-design methodology adapted to SoC FPGA-based controllers for embedded power applications. The case study is a sensorless current controller of a synchronous machine using an extended Kalman filter (EKF). This co-design development is based on two reference implementations: a full software implementation and a full hardware implementation that are also discussed. To find the optimal HW/SW partitioning, a non-dominated sorting genetic algorithm (NSGA-II) is used.

A general algorithm of a Space Vector approach is implemented on a 6-leg VSI controlling a PM synchronous machine with three independent phases. In this last case, the necessity of controlling the zero-sequence current motivates the choice of a special family of vectors, different of this one used in Pulse Width Modulation (PWM) intersective strategy and in common Space Vector PWM (SVPWM). To preserve the parallelism of the algorithm and fulfill the execution time constraints, the implementation is made on a Field Programmable Gate Array (FPGA). Comparisons with more classical 2-level and 3-level PWM are provided. Fui8 within the SOFRACI project

The aim of this paper is to present a FPGA (Field Programmable Gate Array (FPGA) based implementation of sensorless speed controllers for an embedded aircraft electrical system composed of a Brushless Synchronous Starter/Generator (BSSG). To eliminate the mechanicals sensors, the proposed strategy provides position estimation based on two sensorless approaches depending. For very low speed and standstill, the injection of a rotating high frequency voltage in the vector control scheme is validated experimentally with BSSG. For low and high speed, an Extended Kalman Filter (EKF) algorithm is used. As first step of validation, the experimental results were performed with a Standard Synchronous Actuator (SSA). Experimental results prop up the efficiency and the interest of using FPGAs in such application. In order to evaluate the features of a system-on-chip (SoC) approach integrating a soft processor core, a HW-SW (Hardware-Software) partitioning has been performed using the EKF-based sensorless speed controller. An optimization algorithm NSGA-II (Non-dominated Sorting Genetic Algorithm) is used to find the optimal partitioning of control modules regarding constraints (time/area).

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs.

Sensorless control of synchronous machine (SM) is a well-investigated research topic. However, avionics manufacturers still have restrictions about its applications due to the complexity of the on-board systems. This study presents a study investigating the use of an extended Kalman filter (EKF) to estimate the position and speed of a brushless exciter synchronous starter/generator. In spite of the machine complexity and the critical choice of the EKF covariance matrices, the EKF observer presents satisfying simulation results in estimating the position and the velocity of the mentioned motor during the start-up. Experimental results performed on an SM with an EKF implemented on a field programmable gate array are also shown to prove the efficiency of this type of implementation.

This paper presents an efficient and well structured design methodology for designing complex FPGA (Field Programmable Gate Array) based controllers. To illustrate the interest and the particularity of this methodology, a complex sensorless control algorithm for a synchronous machine has been chosen. This algorithm consists of an Extended Kalman Filter (EKF) which is used to estimate rotor position and speed. In this paper, the whole design methodology steps are discussed. For the developed application, a preliminary system specification is made. Then, the algorithm development and the FPGA-based architecture development are separately presented. Finally the experimental validation is presented.

This paper presents a Field Programmable Gate Array (FPGA) based sensorless speed controller for a Synchronous Machine (SM). The implemented algorithm uses an Extended Kalman Filter (EKF) to estimate the rotor position and speed. Due to the intensive EKF treatment, the optimization of the algorithm complexity and the FPGA consumed resources has been achieved and the adopted optimization procedures have been discussed. Experimental results are provided in order to prop up the efficiency and the interest of using FPGAs in such application.

This paper presents a short state-of-the-art Field Programmable Gate Array (FPGA) technology. An efficient design methodology for designing FPGA-based controllers is also described. To illustrate the interest of this methodology, a complex sensorless algorithm for AC drives has been chosen. It consists in an Extended Kalman Filter (EKF), which is most of the time implemented in a DSP controller. In the last part of the paper, authors try to demonstrate all the benefits of using FPGAs for power electronic and drive applications. Two cases are discussed, the high demanding applications and the constrained switching frequency applications.

The use of Extended Kalman Filter (EKF) as a velocity and position nonlinear observer for synchronous motors is a mature research topic. Notwithstanding, the application of EKF in the aircraft domain is still restricted due to the complexity of the systems. This paper presents a study for using an EKF to estimate the position and speed of a brushless exciter synchronous starter/generator in electrical aircrafts. This type of machine is commonly used in this domain due to its autonomy, robustness and dual functioning. In spite of the machine complexity and the critical choice of the EKF covariance matrices, the EKF observer presents satisfying simulation results in estimating the position and the velocity of the mentioned motor during the starting operation. This is promising for the implementation and its use in the aircraft domain.

The aim of this paper is to present a fully FPGA (Field Programmable Gate Array) based Sensorless Controller for a Synchronous Motor (SM). The estimation of the rotor position and speed is achieved using an Extended Kalman Filter (EKF). The drive also incorporates a PI-based controller for stator currents and a hysteresis-based controller for rotor current. The objective of this work is to prove the ability of a FPGA to ensure the required performances in terms of execution time, consumed resources and sensorless control quality. The developed architecture of the EKF is presented and a discussion about the time/area performances is made. Some experimental results are provided in order to prove the reliability and the efficiency of the developed control system.

The aim of this paper is to present a fully integrated solution for synchronous motor control. The implemented controller is based on Actel Fusion field-programmable gate array (FPGA). The objective of this paper is to evaluate the ability of the proposed fully integrated solution to ensure all the required performances in such applications, particularly in terms of control quality and time/area performances. To this purpose, a current control algorithm of a permanent-magnet synchronous machine has been implemented. This machine is associated with a resolver position sensor. In addition to the current control closed loop, all the necessary motor control tasks are implemented in the same device. The analog-to-digital conversion is ensured by the integrated analog-to-digital converter (ADC), avoiding the use of external converters. The resolver processing unit, which computes the rotor position and speed from the resolver signals, is implemented in the FPGA matrix, avoiding the use of external resolver-to-digital converter (RDC). The sine patterns used for the Park transformation are stored in the integrated flash memory blocks.

This paper presents the implementation of a system on chip (SoC) controller for a synchronous machine using a fusion field programmable gate array (FPGA). This component integrates, in addition to an FPGA matrix, analog peripherals such as, analog to digital converter (ADC), analog prescalers and an analog multiplexer for multi-channel conversion. Thus, in such application and in order to improve the control quality, a compensation of the ADC non-linearity error is achieved. Moreover, sampling synchronization error (SSE) compensation is implemented in order to minimize the impact of the serialized conversion process. Besides this ADC errors compensation, and always in perspective to improve the control quality, the voltage source inverter (VSI) non-linearity error compensation is implemented. This VSI error is mainly due to the introduced dead time, to power switches turn-on/off delays and also to the voltage drops. Simulations and experimental results are given to illustrate the efficiency of the developed compensation methods.

The aim of this paper is to present a full system on chip (SoC) solution for electrical actuator control. The implemented controller is based on Actel fusion field programmable gate array (FPGA). The objective of this work is to evaluate the ability of the proposed SoC solution to ensure all the required performances in such applications, especially in terms of integration capacity and time/area performances. To this purpose, a current control algorithm for a permanent magnet synchronous machine (PMSM) has been implemented. This machine is associated with a resolver position sensor. In addition to the current control closed-loop, all the necessary motor control tasks are implemented in the same SoC fusion device. The analog to digital conversion is ensured by the integrated analog to digital converter (ADC) avoiding the use of external converters. The resolver processing unit (RPU), which computes the rotor position and speed from the resolver signals, is implemented in the FPGA matrix, avoiding the use of external resolver to digital converter (RDC). The sine patterns used for the Park transformation are stored in the integrated flash memory blocks.

This paper presents a comparison between a standard FPGA-based controller and a full FPGA-based controller for electrical systems. The first controller uses a standard low cost FPGA such as Xilinx Spartan and the second one uses an Actel Fusion FPGA which integrates all the peripherals required for these kinds of applications. The purpose here, is to analyze in details the potential benefits offered by this last solution compared to the first one. To this purpose, a current control algorithm for AC drives has been implemented on both targets. This comparison concerns the design methodology (evaluation of the reusability of designs), the time/area performances and also the quality of the system control.

Their importance and reliability make resolvers key building blocks in flight control and navigation dynamics. This paper gives an overview of the different synchronous demodulation methods, for such devices and lists advantages and drawbacks for each one. A particular attention is given to implantation in the same device of both analog to digital converter (ADC) and algorithm. This true system on a chip (SoC) solution is realized by the fusion field programmable gate array (FPGA) from Actel Company.

This paper presents the implementation of a current control for synchronous machine using the fusion field programmable gate array (FPGA) from Actel Company. This component integrates analog peripherals such as ADC and also flash memory blocks, in a single chip. The achieved implementation allows evaluating the efficiency and the integration capacity of a true system on a chip (SoC) solution. An overview of the fusion FPGA architecture is firstly given, followed by the description of the current control algorithm. In addition, this paper presents some experimental results enabling to illustrate the benefits of this fully integrated solution.